Memory device and semiconductor device

ABSTRACT

To provide a memory device which operates at high speed or a memory device in which the frequency of refresh operations is reduced. In a cell array, a potential is supplied from a driver circuit to a wiring connected to a memory cell. The cell array is provided over the driver circuit. Each of memory cells included in the cell array includes a switching element, and a capacitor in which supply, holding, and discharge of electric charge are controlled by the switching element. Further, a channel formation region of the transistor used as the switching element includes a semiconductor whose band gap is wider than that of silicon and whose intrinsic carrier density is lower than that of silicon.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.15/462,077, filed Mar. 17, 2017, now allowed, which is a continuation ofU.S. application Ser. No. 13/350,086, filed Jan. 13, 2012, now U.S. Pat.No. 9,601,178, which claims the benefit of foreign priority applicationsfiled in Japan as Serial No. 2011-013908 on Jan. 26, 2011, and SerialNo. 2011-108895 on May 14, 2011, all of which are incorporated byreference.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to a memory device and a semiconductordevice including the memory device.

2. Description of the Related Art

In portable electronic devices such as a mobile phone, a smartphone, andan e-book reader, a semiconductor memory device (hereinafter, alsosimply referred to as a memory device) such as static random accessmemory (SRAM) or dynamic random access memory (DRAM), which writes andreads data at high speed, is used so as to store image data temporarily.In order to increase operation speed of the memory device, in the caseof SRAM, it is effective to increase switching speed of transistors byminiaturization because data is stored with the use of flip-flopsincluding a plurality of transistors. However, in the case of DRAM, datais stored by supply of electric charge to a capacitor; accordingly, anincrease in switching speed of a transistor controlling supply ofelectric charge is not greatly effective to operation speed in writingand reading data.

Patent Document 1 discloses a semiconductor memory device in which twoword lines are connected to each other at a word line parallelconnecting point to reduce wiring resistance from that of a conventionalcircuit, so that delay in word lines is solved.

REFERENCE

[Patent Document 1] Japanese Patent Published Application No. H5-266670

SUMMARY OF THE INVENTION

As described in Patent Document 1, a decrease in resistance of wiringssuch as a word line allows an increase in writing and reading speed.However, in order to increase in writing and reading speed in thesemiconductor memory device described in Patent Document 1, a ratio ofthe number of memory cells to the number of wirings such as bit linesand word lines needs to be increased. Accordingly, the yield is likelyto be decreased because of defects such as a break and a short in awiring due to dust or failure in etching. In addition, an increase inthe number of wirings results in an increase in the area of the cellarray.

DRAM is advantageous for large storage capacity as compared to othermemory devices; however, memory capacity per unit area needs to befurther increased as in other memory devices in order that an LSI havinghigher degree of integration is realized while an increase in a chipsize is suppressed. However, when the area of a memory cell is reduced,the capacitance value is decreased due to a reduction in the area of acapacitor; therefore, difference of the amount of electric chargebetween the digital values becomes smaller and the frequency of refreshoperations needs to be increased. Further, when the number of refreshoperations is increased, power consumption of a memory device isincreased and reliability is lowered because of deterioration of atransistor. In particular, when the transistor is miniaturized to reducethe area of the memory cell, the decrease in reliability is remarkable.

An object of the present invention is to provide a memory device whichoperates at high speed. An object of the present invention is to providea memory device in which a frequency of refresh operations is reduced.

An object of the present invention is to provide a semiconductor devicewhich operates at high speed. An object of the present invention is toprovide a semiconductor device in which storage capacitance per unitarea of a memory device is increased and a decrease in reliability isprevented.

In a memory device according to an embodiment of the present invention,any of memory cells among a plurality of memory cells in a cell array isconnected to a wiring such as a word line or a data line. In anembodiment of the present invention, a potential generated at the drivercircuit is supplied to the wiring such as a word line or a data line notfrom the outside of the cell array but from the inside of the cell arrayor between two memory cells among the plurality of memory cellsconnected to a wiring.

Therefore, in an embodiment of the present invention, focusing on awiring, a distance between points (power feeding points) can be short.One of the points is a point in which a potential is supplied from thedriver circuit to the wiring and the other of the points is a point inwhich a potential is supplied from the wiring to a memory cell providedin the edge portion of the cell array. Accordingly, even when thepotential of the wiring drops because of the resistance of the wiring,the potential difference between the two points can be small.

Note that in the case where the wiring is a word line, the potential ofa signal for selecting a memory cell is supplied from the driver circuitto the word line. In the case where the wiring is a data line, thepotential of a signal including data is supplied from the driver circuitto the data line.

In an embodiment of the present invention, a cell array is provided overa driver circuit. A plurality of memory cells included in the cell arrayeach include a switching element, and a capacitor in which supply,holding, and discharge of electric charge are controlled by theswitching element. Further, a channel formation region of the transistorused as the switching element includes a semiconductor whose band gap iswider than that of silicon and whose intrinsic carrier density is lowerthan that of silicon. As such a semiconductor, for example, an oxidesemiconductor, silicon carbide, gallium nitride, or the like which hasapproximately twice or more as wide band gap as silicon can be given. Atransistor including the semiconductor can have much lower off-statecurrent than a transistor including a normal semiconductor material suchas silicon or germanium. The transistor having the above structure isused as a switching element for holding charge flowing into a capacitor,whereby leakage of electric charge from the capacitor can be prevented.

A purified oxide semiconductor (purified OS) obtained by reduction ofimpurities such as moisture or hydrogen which serves as an electrondonor (donor) and by reduction of oxygen defects is an intrinsic(i-type) semiconductor or a substantially i-type semiconductor.Therefore, a transistor including the oxide semiconductor has acharacteristic of extremely low off-state current. Specifically, theconcentration of hydrogen in the highly-purified oxide semiconductorthat is measured by secondary ion mass spectrometry (SIMS) is less than5×10¹⁸/cm³ or lower, preferably less than or equal to 5×10¹⁷/cm³, morepreferably less than or equal to 1×10¹⁶/cm³. In addition, the carrierdensity of the oxide semiconductor film that can be measured by Halleffect measurement is lower than 1×10¹⁴/cm³, preferably lower than1×10¹²/cm³, more preferably lower than 1×10¹¹/cm³. Furthermore, the bandgap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV ormore, more preferably 3 eV or more. With the use of the oxidesemiconductor film which is purified by sufficiently reducing theconcentration of impurities such as moisture and hydrogen, off-statecurrent of the transistor can be reduced.

The analysis of the concentration of hydrogen in the oxide semiconductorfilm is described here. The concentration of hydrogen in thesemiconductor film is measured by SIMS. It is known that it is difficultto obtain accurate data in the proximity of a surface of a sample or inthe proximity of an interface between stacked films formed usingdifferent materials by the SIMS in principle. Thus, in the case wherethe distribution of the hydrogen concentration of the film in athickness direction is analyzed by SIMS, an average value in a region ofthe film, in which the value is not greatly changed and almost the samevalue can be obtained is employed as the hydrogen concentration.Further, in the case where the thickness of the film to be measured issmall, a region where substantially the same value can be obtainedcannot be found in some cases due to the influence of the hydrogenconcentration of other films adjacent to the top and the bottom of thefilm. In that case, the maximum value or the minimum value of thehydrogen concentration in the region of the film is used as the hydrogenconcentration of the film. Further, in the case where a mountain-shapedpeak having the maximum value or a valley-shaped peak having the minimumvalue do not exist in the region of the film, the value at theinflection point is employed as the hydrogen concentration.

Various experiments can actually prove low off-state current of thetransistor including the highly-purified oxide semiconductor film as anactive layer. For example, even when an element has a channel width of1×10⁶ μm and a channel length of 10 μm, off-state current can be lowerthan or equal to the measurement limit of a semiconductor parameteranalyzer, i.e., lower than or equal to 1×10⁻¹³ A, at voltage (drainvoltage) between the source electrode and the drain electrode of from 1V to 10 V. In this case, an off-state current density corresponding to avalue obtained by dividing the off-state current by the channel width ofthe transistor is lower than or equal to 100 zA/μm. Further, anoff-state current density was measured by use of a circuit in which acapacitor and the transistor are connected to each other and electriccharge which is supplied to or discharged from the capacitor iscontrolled by the transistor. In the measurement, the highly-purifiedoxide semiconductor film was used as a channel formation region in thetransistor, and change in the amount of electric charge of the capacitorper unit time is measured to obtain the off-state current density of thetransistor. As a result, in the case where the voltage between thesource electrode and the drain electrode of the transistor was 3 V, alower off-state current density of several tens yoctoampere permicrometer (yA/μm) was able to be obtained. Accordingly, the transistorincluding the highly-purified oxide semiconductor film as an activelayer has much lower off-state current than a transistor includingsilicon having crystallinity.

Unless otherwise specified, in the case of an n-channel transistor, anoff-state current in this specification is current which flows between asource electrode and a drain electrode when the potential of the drainelectrode is higher than that of the source electrode and that of a gateelectrode while the potential of the gate electrode is less than orequal to zero when a reference potential is the potential of the sourceelectrode. Further, in this specification, in the case of a p-channeltransistor, an off-state current is current which flows between a sourceelectrode and a drain electrode when the potential of the drainelectrode is lower than that of the source electrode and that of a gateelectrode while the potential of the gate electrode is greater than orequal to zero when a reference potential is the potential of the sourceelectrode.

As the oxide semiconductor, for example, an indium oxide, a tin oxide, azinc oxide, a two-component metal oxide such as an In—Zn-based oxide, aSn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, aSn—Mg-based oxide, an In—Mg-based oxide, or an In—Ga-based oxide, athree-component metal oxide such as an In—Ga—Zn-based oxide (alsoreferred to as IGZO), an In—Al—Zn-based oxide, an In—Sn—Zn-based oxide,a Sn—Ga—Zn-based oxide, an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide,an In—Hf—Zn-based oxide, an In—La—Zn-based oxide, an In—Ce—Zn-basedoxide, an In—Pr—Zn-based oxide, an In—Nd—Zn-based oxide, anIn—Sm—Zn-based oxide, an In—Eu—Zn-based oxide, an In—Gd—Zn-based oxide,an In—Tb—Zn-based oxide, an In—Dy—Zn-based oxide, an In—Ho—Zn-basedoxide, an In—Er—Zn-based oxide, an In—Tm—Zn-based oxide, anIn—Yb—Zn-based oxide, or an In—Lu—Zn-based oxide, a four-component metaloxide such as an In—Sn—Ga—Zn-based oxide, an In—Hf—Ga—Zn-based oxide, anIn—Al—Ga—Zn-based oxide, an In—Sn—Al—Zn-based oxide, anIn—Sn—Hf—Zn-based oxide, or an In—Hf—Al—Zn-based oxide can be used. Theabove oxide semiconductor may include silicon.

In this specification, an In—Ga—Zn-based oxide means, for example, anoxide including In, Ga, and Zn, and there is no limitation on the ratioof In:Ga:Zn. Further, the In—Ga—Zn-based oxide may contain a metalelement in addition to In, Ga, and Zn. Note that an In—Ga—Zn—O-basedoxide has sufficiently high resistance when there is no electric fieldand thus off-state current can be sufficiently reduced. Moreover, alsohaving high field-effect mobility, the In—Ga—Zn-based oxide is suitablefor a semiconductor material used in a semiconductor device.

In an embodiment of the present invention, a difference between suppliedpotentials between a plurality of memory cells connected to one wiringcan be small within a short time, whereby speed of operations such aswriting or reading data can be increased.

In an embodiment of the present invention, a cell array is provided overa driver circuit, so that the size of a whole memory device includingthe driver circuit and the cell array can be small. Further, asdescribed above, a transistor with extremely low off-state current isused as a switching element, whereby leakage of electric charge from acapacitor can be prevented and the frequency of refresh operations canbe low. Therefore, power consumption of the memory device can be smalland a reduction in reliability due to deterioration of transistor can beprevented. In addition, a reduction in frequency of refresh operationsachieves high-speed operation of the memory device and the semiconductordevice.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a structure of a memory device.

FIG. 2 is a circuit diagram of a cell array.

FIG. 3 is a timing diagram of operation of the cell array.

FIG. 4 is a block diagram illustrating a structure of a memory device.

FIG. 5 illustrates a structure of a reading circuit.

FIGS. 6A to 6D illustrate a method for manufacturing a memory device.

FIGS. 7A to 7C illustrate a method for manufacturing a memory device.

FIGS. 8A to 8C illustrate the method for manufacturing a memory device.

FIGS. 9A to 9D each illustrate a structure of a transistor.

FIGS. 10A to 10D each illustrate a structure of a transistor.

FIGS. 11A to 11C each illustrate an electronic device.

FIG. 12 is a cross-sectional view of a memory device.

FIGS. 13A to 13E are examples of an oxide semiconductor.

FIGS. 14A to 14C are examples of an oxide semiconductor.

FIGS. 15A to 15C are examples of an oxide semiconductor.

FIG. 16 illustrates a relation between gate voltage and mobility.

FIGS. 17A to 17C each illustrate a relation between gate voltage anddrain current.

FIGS. 18A to 18C each illustrate a relation between gate voltage anddrain current.

FIGS. 19A to 19C each illustrate a relation between gate voltage anddrain current.

FIGS. 20A to 20C each illustrate the characteristics of a transistor.

FIGS. 21A and 21B each illustrate the characteristics of a transistor.

FIGS. 22A and 22B each illustrate the characteristics of a transistor.

FIG. 23 illustrates the temperature dependence of off-state current of atransistor.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments of the present invention will be described indetail with reference to the accompanying drawings. However, the presentinvention is not limited to the following description and it is easilyunderstood by those skilled in the art that the mode and details can bevariously changed without departing from the scope and spirit of thepresent invention. Accordingly, the invention should not be construed asbeing limited to the description of the embodiments below.

The present invention includes in its category the following variouskinds of semiconductor devices in which a memory device can be used:integrated circuits such as microprocessors, image processing circuits,digital signal processors (DSPs), and microcontrollers, memory devicessuch as RF tags and memory cards, and semiconductor display devices. Thesemiconductor display devices include the following in its category:liquid crystal display devices, light-emitting devices in which alight-emitting element typified by an organic light-emitting element(OLED) is provided for each pixel, electronic paper, digital micromirrordevices (DMDs), plasma display panels (PDPs), field emission displays(FEDs), and other semiconductor display devices in which a circuitelement using a semiconductor film is included in a driver circuit.

Embodiment 1

FIG. 1 illustrates the structure of the memory device according to anembodiment of the present invention. The memory device illustrated inFIG. 1 includes a cell array 101 in which a plurality of memory cells100 are arranged in matrix and a driver circuit 102 provided below thecell array 101.

Further, in the cell array 101, a plurality of wirings for supplyingpotentials to the memory cell 100 are provided. Specifically, aplurality of word lines WL and a plurality of data lines DL are providedfor the cell array 101 illustrated in FIG. 1.

Note that the number of the wirings can be determined by the number ofthe memory cells 100 and arrangement of the memory cells 100 in the cellarray 101. Specifically, FIG. 1 illustrates an example in the case wherethe memory cells 100 in x rows and y columns are connected in matrix andthe word lines WL1 to WLy and the data lines DL1 to DLx are arranged inthe cell array 101. Further, each of the memory cells 100 is connectedto one of the plurality of data lines DL1 to DLx and one of theplurality of word lines WL1 to WLy.

The driver circuit 102 includes at least a word line driver circuit 103which selects the word line WL by supply of a potential to the word lineWL, and a data line driver circuit 104 which controls writing of data tothe memory cell 100 connected to the selected word line WL. Further, thedata line driver circuit 104 may include a reading circuit for readingdata.

The word line driver circuit 103 and the data line driver circuit 104can control operations such as writing of data to the cell array 101,reading of data from the cell array 101, holding of data in the cellarray 101, or the like in accordance with a signal from the controlcircuit. Note that in FIG. 1, the control circuit which supplies asignal to the word line driver circuit 103 and the data line drivercircuit 104 is not included in the driver circuit 102 and is assumed tobe provided outside the memory device; however, the control circuit canbe included as a component of the driver circuit 102.

The potential of a signal from the driver circuit 102 is supplied toeach of the memory cells 100 through the plurality of word lines WL andthe plurality of data lines DL. Specifically, the potential of a signalfrom the word line driver circuit 103 is supplied to the word lines WL.The potential supplied to one of the word lines WL is supplied to theplurality of memory cells 100 for one row connected to the one of theword lines WL. The potential of a signal from the data line drivercircuit 104 is supplied to the data lines DL. The potential supplied toone of the data lines DL is supplied to the selected memory cell(s) 100among the plurality of memory cells 100 for one column connected to theone of the data lines DL.

In an embodiment of the present invention, the potential generated atthe driver circuit is supplied to wirings such as a word line WL, a dataline DL, or the like, not from the outside of the cell array 101 butfrom the inside of the cell array 101 or between the memory cells 100.Specifically, FIG. 1 illustrates the case where the potential of asignal from the word line driver circuit 103 is supplied to the wordlines WL1 to WLy between the memory cells 100 connected to the data lineDL4 and the memory cells 100 connected to the data line DL(x−3). FIG. 1illustrates the case where the potential of a signal from the data linedriver circuit 104 is supplied to the data lines DL1 to DLx between thememory cells 100 connected to the word line WL4 and the memory cells 100connected to the word line WL(y−3).

In FIG. 1, a power feeding point 105, in which a potential is suppliedfrom the word line driver circuit 103 to the word lines WL1 to WLy, isdenoted by a white circle. Further, a power feeding point 106, in whicha potential is supplied from the data line driver circuit 104 to thedata lines DL1 to DLx, is denoted by a white circle.

Note that FIG. 1 illustrates the case where the power feeding point 105and the power feeding point 106 are provided between the memory cells100; however, in an embodiment of the present invention, at least thepower feeding point 105 or the power feeding point 106 may be providedin the cell array 101.

Further, FIG. 1 illustrates the case where the power feeding point 105and the power feeding point 106 are provided inside the cell array 101;however, in an embodiment of the present invention, either the powerfeeding point 105 or the power feeding point 106 may be provided in thecell array 101.

Note that a plurality of conductive films which are in contact with oneanother can function as one wiring. Further, one conductive film canfunction as both a wiring and an electrode of a semiconductor element.Therefore, it is difficult to completely distinguish one wiring from theother components. In this specification, the position of a power feedingpoint in which a potential is supplied from the driver circuit to awiring can be regarded as the position of a contact hole, in which thedriver circuit and the wiring are connected and which is provided in aninsulating film provided between a layer in which the driver circuit 102is formed and a layer in which the cell array 101 is formed.

For example, points in which a potential is supplied from the word lineWL1 to the memory cells 100 in the first column and the x-th columnwhich are in the edge portions of the cell array 101, among the memorycells 100 connected to the word line WL1, are referred to as a powerfeeding point 107 and a power feeding point 108, respectively. In thecase of a conventional structure in which a potential is supplied fromthe outside of the cell array 101 to the word line WL or the data lineDL, a power feeding point X (not shown) for supplying a potential fromthe word line driver circuit 103 to the word line WL1 is placed at theedge portion of the cell array 101. Therefore, there is a greatdifference between a distance between the power feeding point X and thepower feeding point 107 and a distance between the power feeding point Xand the power feeding point 108. On the other hand, in the case of anembodiment of the present invention, a potential is supplied to the wordlines WL or the data lines DL not from the outside of the cell array 101but from the inside of the cell array 101 or between the memory cells100. Therefore, focusing on the word line WL1, the power feeding point105 in which a potential is supplied to the word line WL1 from the wordline driver circuit 103 is in the cell array 101; thus, a differencebetween a distance between the power feeding point 105 and the powerfeeding point 107 and a distance between the power feeding point 105 andthe power feeding point 108 is smaller than the case of the conventionalstructure. Therefore, even when the potential of the word line WL1 dropsbecause of the resistance of the word line WL1, a potential differencebetween the power feeding point 107 and the power feeding point 108 canbe small in comparison with the case of the conventional structure.

Similarly, in the case of the word lines WL other than the word line WL1and the data lines DL, a potential difference between a power feedingpoint in which a potential is supplied to the wirings from the drivercircuit 102 and a power feeding point in which a potential is suppliedto the memory cell 100 placed in the edge portion of the cell array 101from the wirings can be small. Accordingly, a potential differencebetween power feeding points of the memory cells 100 in the edge portioncan be small.

Accordingly, a difference between supplied potentials between aplurality of memory cells 100 connected to one word line WL or data lineDL can be small within a short time, whereby the speed of operationssuch as writing or reading data can be increased.

In an embodiment of the present invention, the cell array 101 isprovided over the driver circuit 102, whereby the size of the wholememory device including the driver circuit 102 and the cell array 101can be small.

Next, FIG. 2 illustrates a specific example of a circuit diagram of thecell array 101 illustrated in FIG. 1. Wirings such as the plurality ofword lines WL, the plurality of data lines DL, and a plurality ofcapacitor lines CL are provided in the cell array 101 illustrated inFIG. 2. The potential of a signal from the driver circuit or a powersupply potential is supplied to each of the memory cells 100 through theabove wirings.

Specifically, in FIG. 2, the power feeding point 105, in which apotential is supplied from the word line driver circuit to the wordlines WL1 to WLy, is denoted by a white circle. Further, the powerfeeding point 106, in which a potential is supplied from the data linedriver circuit to the data lines DL1 to DLx, is denoted by a whitecircle.

Each memory cell 100 includes a transistor 109 serving as a switchingelement and a capacitor 110. The memory cell 100 in FIG. 2 stores databy accumulating electric charge in the capacitor 110.

Note that the terms a “source terminal” and a “drain terminal” of atransistor interchange with each other depending on the polarity of thetransistor or a difference between levels of potentials applied to theelectrodes. In general, in an n-channel transistor, an electrode towhich a lower potential is applied is called a source terminal, and anelectrode to which a higher potential is applied is called a drainterminal Further, in a p-channel transistor, an electrode to which alower potential is applied is called a drain terminal, and an electrodeto which a higher potential is applied is called a source terminal.Hereinafter, one of a source terminal and a drain terminal is referredto as a first terminal and the other is referred to as a secondterminal, and a connection relationship of the transistor 109 and thecapacitor 110 included in the memory cell 100 is described.

Specifically, a first terminal of the transistor 109 is connected to oneof the data lines DL. A gate electrode of the transistor 109 isconnected to one of the word lines WL. One of the pair of electrodes ofthe capacitor 110 that is not connected to the second terminal of thetransistor 109 is connected to one of the capacitor lines CL.

Note that the memory cell 100 may further include another circuitelement such as a transistor, a diode, a resistor, a capacitor, or aninductor when needed.

Note that the number of the wirings can be determined by the number ofthe memory cells 100 and arrangement of the memory cells 100.Specifically, the cell array 101 illustrated in FIG. 2 illustrates thecase where the memory cells 100 in x columns and y rows are connected inmatrix, and the word lines WL1 to WLy, the data lines DL1 to DLx, andthe capacitor lines CL1 to CLy are arranged in the cell array 101.

Note that the “source terminal” of the transistor means a source regionor a source electrode. Similarly, the “drain terminal” of the transistormeans a drain region or a drain electrode.

In this specification, the “connection” means electrical connection andcorresponds to the state in which current, voltage, or a potential canbe supplied or transmitted. Accordingly, a connection state does notalways mean a direct connection state but includes an indirectconnection state through an element such as a wiring, a conductive film,a resistor, a diode, or a transistor so that current, voltage, or apotential can be supplied or transmitted.

In addition, even when different components are connected to each otherin a circuit diagram, there is actually a case where one conductive filmhas functions of a plurality of components such as a case where part ofa wiring serves as an electrode. The term “connection” also means such acase where one conductive film has functions of a plurality ofcomponents.

Although FIG. 2 illustrates examples of the case where the transistor109 has a single-gate structure, the transistor 109 may have amulti-gate structure in which a plurality of electrically connected gateelectrodes are included so that a plurality of channel formation regionsare included.

In an embodiment of the present invention, a channel formation region ofthe transistor 109 functioning as a switching element includes asemiconductor material whose band gap is wider than that of silicon andwhose intrinsic carrier density is lower than that of silicon. With achannel formation region including a semiconductor material having theabove characteristics, the transistor 109 whose off-state current isextremely low can be realized.

In the case where data is stored by control of the amount of electriccharge as the memory cell 100 illustrated in FIG. 2, supply of electriccharge to the memory cell 100, discharge of electric charge from thememory cell 100, and holding of electric charge in the memory cell 100are controlled with the use of the transistor 109 functioning as aswitching element. Thus, the length of a data holding time depends onthe amount of leakage of electric charge accumulated in the memory cell100, through the transistor 109. In an embodiment of the presentinvention, the off-state current of the transistor 109 can be extremelylow as described above. Thus, the electric charge can be prevented fromleaking, so that the data holding time can be made longer. Accordingly,the frequency of refresh operations can be low, so that powerconsumption of a memory device can be low and a decrease in reliabilitydue to deterioration of transistor can be prevented; furthermore, amemory device and a semiconductor device can operate at high speed.

Note that as one example of a semiconductor whose band gap is wider thanthat of a silicon semiconductor and whose intrinsic carrier density islower than that of silicon, a compound semiconductor such as siliconcarbide (SiC) or gallium nitride (GaN), an oxide semiconductor formed ofmetal oxide such as zinc oxide (ZnO), or the like can be used. Compoundsemiconductors such as silicon carbide and gallium nitride are requiredto be single crystal, and it is difficult to meet the fabricatingcondition to obtain a single crystal material; for example, crystalgrowth at a temperature extremely higher than a process temperature ofthe oxide semiconductor is needed or epitaxial growth over a specialsubstrate is needed. In addition, it is difficult to form such compoundsemiconductors over a silicon wafer or a glass substrate with low heatresistance, which can be obtained easily. On the contrary, the oxidesemiconductor has the advantage that it can be formed by a sputteringmethod or a wet method (a printing method or the like) and has good massproductivity. Further, an oxide semiconductor can be formed at a roomtemperature, so that the oxide semiconductor can be formed over a glasssubstrate, or over an integrated circuit including a semiconductorelement, and a larger substrate can be used. Accordingly, among thesemiconductors with wide band gaps, the oxide semiconductor particularlyhas an advantage of high mass productivity. Further, in the case where acrystalline oxide semiconductor is used in order to improve the propertyof a transistor (e.g., mobility), the crystalline oxide semiconductorcan be obtained by heat treatment at 200° C. to 800° C.

In the following description, an example in which an oxide semiconductorwith the above advantages is used as a semiconductor film of thetransistor 109 is given.

Note that although in FIG. 2, the memory cell 100 includes onetransistor 109 functioning as a switching element, the present inventionis not limited to this structure. In an embodiment of the presentinvention, it is acceptable as long as one transistor which functions asa switching element is provided in each memory cell, and the number ofsuch transistors may be plural. In the case where the memory cell 100includes a plurality of transistors serving as switching elements, theplurality of transistors may be connected to each other in parallel, inseries, or in combination of parallel connection and series connection.

Note that in this specification, the state in which the transistors areconnected to each other in series means, for example, the state in whichonly one of a first terminal and a second terminal of a first transistoris connected to only one of a first terminal and a second terminal of asecond transistor. Further, the state in which the transistors areconnected to each other in parallel means a state in which the firstterminal of the first transistor is connected to the first terminal ofthe second transistor and the second terminal of the first transistor isconnected to the second terminal of the second transistor.

Further, the transistor 109 includes at least a gate electrode on oneside of an active layer, but may include a pair of gate electrodes withthe active layer provided therebetween. In that case, one of the gateelectrodes is supplied with a signal for controlling switching, and theother of the gate electrodes (a back gate electrode) may be in afloating state (i.e., electrically isolated) or may be supplied with apotential. In the latter case, potentials at the same level may beapplied to the pair of electrodes, or a fixed potential such as a groundpotential may be applied only to the back gate electrode. The level ofthe potential supplied to the back gate electrode is controlled, wherebythe threshold voltage of the transistor 109 can be controlled.

Note that in an embodiment of the present invention, a wide-gapsemiconductor material such as an oxide semiconductor may be included atleast in an active layer of the transistor 109 which functions as aswitching element. On the other hand, for an active layer of thetransistor included in the driver circuit, an oxide semiconductor may beused or the following semiconductor other than the oxide semiconductormay be used: amorphous silicon, microcrystalline silicon,polycrystalline silicon, single crystal silicon, amorphous germanium,microcrystalline germanium, polycrystalline germanium, single crystalgermanium, and the like. Note that when oxide semiconductor films areused for all of the transistors in the memory device, a manufacturingprocess can be simplified. Further, for example, the active layer of thetransistor included in the driver circuit is formed using asemiconductor material such as polycrystalline silicon or single crystalsilicon that has higher mobility than an oxide semiconductor, wherebythe memory device can operate at high speed.

Next, the normal operation of the cell array 101 illustrated in FIG. 2is described with reference to a timing diagram in FIG. 3. Note thatFIG. 3 illustrates the case where data is written to, held in, and readfrom the memory cell 100 in the first column and the first row, thememory cell 100 in the x-th column and the first row, the memory cell100 in the first column and the y-th row, and the memory cell 100 in thex-th column and the y-th row.

The operation of the cell array 101 in the writing period Ta isdescribed. Data is written row by row. FIG. 3 illustrates the case wheredata is written to the memory cell 100 in the first column and the firstrow and the memory cell 100 in the x-th column and the first row, afterthat, data is written to the memory cell 100 in the first column and they-th row and the memory cell 100 in the x-th column and the y-th row.

Note that in the writing period Ta, the ground potential is applied toall of the capacitor lines CL.

First, the word line WL1 connected to the memory cells 100 in the firstrow to which data is written is selected. Specifically, in FIG. 3, thehigh-level potential VH is applied to the word line WL1, and the groundpotential GND is applied to the word lines WL, including the word lineWLy, other than the word line WL1. Thus, only the transistors 109 whosegate electrodes are connected to the word line WL1 are selectivelyturned on.

In a period during which the word line WL1 is selected, potentials ofsignals including data are applied to the data lines DL1 and DLx.Needless to say, the levels of the potentials supplied to the data linesDL1 and DLx are varied depending on the content of the data. FIG. 3illustrates the case where the high-level potential VDD is applied tothe data line DL1 and the ground potential GND is applied to the dataline DLx. The potentials applied to the data lines DL1 and DLx areapplied to one electrode of the capacitor 110 via the transistors 109that are on.

Note that the potential VH is equal to or higher than the potential VDD.Specifically, a potential difference between the potential VH and thepotential VDD is equal to or higher than a threshold voltage of thetransistor 109.

When one electrode of the capacitor 110 is a node FG, the potential ofthe node FG in the memory cell 100 in the first column and the first rowbecomes the potential VDD, and the potential of the node FG in thememory cell 100 in the x-th column and the first row becomes the groundpotential GND in accordance with potentials applied to the data line DL1and the data line DLx. The amount of electric charge supplied to thecapacitor 110 is controlled in accordance with the potential of the nodeFG, whereby data is written to the memory cell 100 in the first columnand the first row and the memory cell 100 in the x-th column and thefirst row.

Next, the ground potential GND is applied to the word line WL1. Thus,the transistors 109 whose gate electrodes are connected to the word lineWL1 are turned off and the electric charge is held in the capacitors110.

Note that in the case where an oxide semiconductor is used for thesemiconductor film of the transistor 109, the transistor 109 has afeature that the off-state current is extremely low. Therefore, theelectric charge held in the capacitors 110 is prevented from leaking,and thus, the data can be held for a long period of time as compared tothe case where a semiconductor such as silicon is used for thetransistor 109.

Next, a word line WLy which is connected to the memory cells 100 in they-th row to which data is written is selected. Specifically, thehigh-level potential VH is applied to the word line WLy and the groundpotential GND is applied to the word lines WL other than the word lineWLy, including the word line WL1, in FIG. 3. Thus, only the transistors109 whose gate electrodes are connected to the word line WLy areselectively turned on.

In a period during which the word line WLy is selected, potentials ofsignals including data are applied to the data lines DL1 and DLx.Needless to say, the levels of the potentials supplied to the data linesDL1 and DLx are varied depending on the content of the data. FIG. 3illustrates the case where the ground potential GND is applied to thedata line DL1 and the high-level potential VDD is applied to the dataline DLx. The potential input to each of the data lines DL1 to DLx isapplied, through each transistor 109 that is on, to one of electrodes ofthe capacitor 110. The potential of the node FG in the memory cell 100in the first column and the y-th row becomes the ground potential GND,and the potential of the node FG in the memory cell 100 in the x-thcolumn and the y-th row becomes the potential VDD in accordance withpotentials applied to the data line DL1 and the data line DLx. Theamount of electric charge supplied to the capacitor 110 is controlled inaccordance with the potential of the node FG, whereby data is written tothe memory cell 100 in the first column and the y-th row and the memorycell 100 in the x-th column and the y-th row.

Next, the ground potential GND is applied to the word line WLy. Thus,the transistors 109 whose gate electrodes are connected to the word lineWLy is turned off and the electric charge is held in the capacitors 110.

In order to prevent writing of erroneous data to the memory cell 100, itis preferable to terminate a supply of a potential including data to thedata line DL after each word line WL is selected.

Next, the operation of the cell array 101 in a data holding period Ts isdescribed.

In the data holding period Ts, the ground potential is applied to all ofthe capacitor lines CL.

In the holding period Ts, a potential in which the transistor 109 isturned off, specifically, the ground potential GND is applied to all ofthe word lines WL. Accordingly, data is held while electric chargesupplied to the capacitor 110 is held.

Then, the operation of the cell array 101 in a data reading period Tr isdescribed.

In the data reading period Tr, the ground potential is applied to all ofthe capacitor lines CL.

In the reading period Tr, an intermediate-level potential VR is appliedto the data line DL connected to the memory cells 100 from which data isread. Specifically, in FIG. 3, the intermediate-level potential VR isapplied to the data line DL1 connected to the memory cells 100 in thefirst column and the data line DLx connected to the memory cells 100 inthe x-th column Note that the potential VR is equal to the potentialVDD, or lower than the potential VDD and higher than the groundpotential GND. After application of the potential VR, the data line DL1and the data line DLx go to a floating-state.

Next, a word line WL1 which is connected to the memory cells 100 in thefirst row from which data is read is selected. Specifically, thehigh-level potential VH is applied to the word line WL1 and the groundpotential GND is applied to the word lines other than the word line WL1,including the word line WLy, in FIG. 3. Thus, only the transistors 109whose gate electrodes are connected to the word line WL1 are selectivelyturned on.

When the transistor 109 is turned on, electric charge held in thecapacitor 110 is discharged to the data line DL which reads data or theelectric charge is supplied from the data line DL which reads data tothe capacitor 110. Operation to be performed is determined in accordancewith the potential of the node FG in the holding period.

Specifically, according to the timing diagram shown in FIG. 3, thepotential of the node FG in the memory cell 100 in the first column andthe first row in the holding period before a reading period is thepotential VDD. Thus, when the transistors 109 are turned on in thereading period, the electric charge is discharged from the capacitor 110in the memory cell 100 in the first column and the first row into thedata line DL1, so that the potential of the data line DL1 increases tobe a potential VR+α. In the holding period before the reading period,the potential of the node FG in the memory cell 100 in the x-th columnand the first row is the ground potential GND. Thus, when thetransistors 109 are turned on in the reading period, the electric chargeis supplied from the data line DLx into the capacitor 110 in the memorycell 100 in the x-th column and the first row, so that the potential ofthe data line DLx decreases to be a potential VR−β.

Therefore, the potential of the data line DL1 and the potential of thedata line DLx depend on the amount of electric charge held in thecapacitor 110 in the memory cell 100 in the first column and the firstrow and the capacitor 110 in the memory cell 100 in the x-th column andthe first row, respectively. Then, by reading a difference in the amountof electric charge from the potential, data can be read from the memorycell 100 in the first column and the first row and the memory cell 100in the x-th column and the first row.

After the data is read from the memory cell 100 in the first column andthe first row and the memory cell 100 in the x-th column and the firstrow, the intermediate-level potential VR is applied again to the dataline DL1 and the data line DLx so that the data line DL1 and the dataline DLx are in the floating state.

Then, the word line WLy which is connected to the memory cells 100 inthe first row from which data is read is selected. Specifically, thehigh-level potential VH is applied to the word line WLy and the groundpotential GND is applied to the word lines other than the word line WLy,including the word line WL1, in FIG. 3. Thus, only the transistors 109whose gate electrodes are connected to the word line WLy are selectivelyturned on.

When the transistor 109 is turned on, electric charge held in thecapacitor 110 is discharged to the data line DL which reads data or theelectric charge is supplied from the data line DL which reads data tothe capacitor 110. Operation to be performed is determined in accordancewith the potential of the node FG in the holding period.

Specifically, according to the timing diagram shown in FIG. 3, thepotential of the node FG in the memory cell 100 in the first column andthe y-th row in the holding period before a reading period is the groundpotential GND. Thus, when the transistors 109 are turned on in thereading period, the electric charge is supplied from the data line DL1into the capacitor 110 in the memory cell 100 in the first column andthe y-th row, so that the potential of the data line DL1 decreases to bethe potential VR−β. In the holding period before the reading period, thepotential of the node FG in the memory cell 100 in the x-th column andthe y-th row is the potential VDD. Thus, when the transistors 109 areturned on in the reading period, the electric charge is discharged fromthe capacitor 110 in the memory cell 100 in the x-th column and the y-throw into the data line DLx, so that the potential of the data line DLxincreases to be the potential VR+α.

Therefore, the potential of the data line DL1 and the potential of thedata line DLx depend on the amount of electric charge held in thecapacitor 110 in the memory cell 100 in the first column and the y-throw and the capacitor 110 in the memory cell 100 in the x-th column andthe y-th row, respectively. Then, by reading a difference in the amountof electric charge from the potential, data can be read from the memorycell 100 in the first column and the y-th row and the memory cell 100 inthe x-th column and the y-th row.

A reading circuit included in the data line driver circuit is connectedto an end of each data line DL, and a signal output from the readingcircuit includes data which is actually read from the cell array 101.

Embodiment 2

An example of a specific structure of the driver circuit in the memorydevice will be described.

FIG. 4 illustrates a block diagram of a specific structure of the memorydevice as an example. In the block diagram in FIG. 4, circuits in thememory device are classified in accordance with their functions andillustrated as separate blocks; however, it is difficult to classifyactual circuits according to their functions completely and one circuitmay have a plurality of functions.

A memory device 800 illustrated in FIG. 4 includes a cell array 801 anda driver circuit 802. The driver circuit 802 includes an input-outputbuffer 803; a word line driver circuit 804 configured to control thepotential of a word line; a data line driver circuit 805 configured tocontrol writing and reading of data to/from a memory cell; and a controlcircuit 806 configured to control operations of the input-output buffer803, the word line driver circuit 804, and the data line driver circuit805.

In the memory device 800 illustrated in FIG. 4, the word line drivercircuit 804 includes a row decoder 807, a level shifter 808, and abuffer 809. The data line driver circuit 805 includes a column decoder810, a level shifter 811, a selector 812, and a reading circuit 813.

Note that the cell array 801, the input-output buffer 803, the word linedriver circuit 804, the data line driver circuit 805, and the controlcircuit 806 may be formed using one substrate; any one of them may beformed using a substrate different from a substrate for the others; orall of them may be formed using different substrates.

In the case where different substrates are used, electrical connectionbetween the substrates can be ensured with the use of an FPC (flexibleprinted circuit) or the like. In that case, part of the driver circuit802 may be connected to an FPC by a COF (chip on film) method. Further,electrical connection can be ensured by a COG (chip on glass) method.

When a signal AD including an address Ax and address Ay of the cellarray 801 as data is input to the memory device 800, the control circuit806 transmits the address Ax in a column direction and the address Ay ina row direction to the data line driver circuit 805 and the word linedriver circuit 804, respectively. In addition, the control circuit 806transmits a signal DATA including data input to the memory device 800 tothe data line driver circuit 805 through the input-output buffer 803.

Operation of writing data and operation of reading data in the cellarray 801 are selected in accordance with a signal RE (read enable), asignal WE (write enable), or the like supplied to the control circuit806. Further, in the case where the plurality of cell arrays 801 areprovided, a signal CE (chip enable) for selecting the cell array 801 maybe input to the control circuit 806. In that case, operation selected inaccordance with the signal RE or the signal WE is performed in the cellarray 801 selected in accordance with the signal CE.

In the cell array 801, when the writing operation is selected inaccordance with the signal WE, a signal for selecting a memory cellcorresponding to the address Ay is generated in the row decoder 807included in the word line driver circuit 804 in response to aninstruction from the control circuit 806. The amplitude of the signal isadjusted by the level shifter 808, and then the processed signal isinput to the cell array 801 through the buffer 809. In the data linedriver circuit 805, a signal for selecting a memory cell correspondingto the address Ax among the memory cells selected in the column decoder810 is generated in response to an instruction from the control circuit806. The amplitude of the signal is adjusted by the level shifter 811,and then the processed signal is input to the selector 812. In theselector 812, the signal DATA is sampled in accordance with the inputsignal, and the sampled signal is input to a memory cell correspondingto the addresses Ax and Ay.

In the cell array 801, when the reading operation is selected inaccordance with the signal RE, a signal for selecting a memory cellcorresponding to the address Ay is generated in the row decoder 807included in the word line driver circuit 804 in response to aninstruction from the control circuit 806. The amplitude of the signal isadjusted by the level shifter 808, and then the processed signal isinput to the cell array 801 through the buffer 809. In the readingcircuit 813, a signal for selecting a memory cell corresponding to theaddress Ax among the memory cells selected in the row decoder 807 isgenerated in response to an instruction from the control circuit 806.Data stored in the memory cell corresponding to the addresses Ax and Ayis read, and a signal including the data is generated.

Note that the data line driver circuit 805 may include a page bufferwhich can temporarily store the signal DATA, a precharge circuit whichsupplies the potential VR in advance to a data line in reading of data,or the like.

This embodiment can be implemented by being combined as appropriate withany of the above embodiments.

Embodiment 3

Next, a specific structural example of the reading circuit will bedescribed.

The levels of potentials read from the cell array are determined inaccordance with data written to the memory cells. Accordingly, ideally,potentials having the same level should be read from the plurality ofmemory cells when data with the same digital value is stored in theplurality of memory cells. However, practically, there is a case wherethe characteristics of as capacitors and transistors which function asswitching elements vary among the memory cells. In that case, thepotentials actually read vary even when all of the data to be read havethe same digital value, so that the levels of the potentials can bewidely distributed. However, even when potentials read from the cellarray vary slightly, a reading circuit can generate a signal includingaccurate data and having an amplitude and a waveform processed inaccordance with a desired specification.

FIG. 5 is a circuit diagram illustrating a structural example of thereading circuit. The reading circuit illustrated in FIG. 5 includestransistors 260 which function as switching elements for controlling theinput of potentials Vdata read from a cell array by the reading circuit.The reading circuit illustrated in FIG. 5 further includes operationalamplifiers 262.

The transistor 260 which functions as a switching element controls thesupply of a potential Vdata to a non-inverting input terminal (+) of theoperational amplifier 262 in accordance with a potential of a signal Sigapplied to a gate electrode of the transistor 260. For example, when thetransistor 260 is turned on, the potential Vdata is applied to thenon-inverting input terminal (+) of the operational amplifier 262. Incontrast, a reference potential Vref is supplied to inverting inputterminals (−) of the operational amplifiers 262. The levels ofpotentials Vout of output terminals can be changed depending on thelevel of the potential applied to the non-inverting input terminals (+)with respect to the reference potential Vref. Thus, a signal whichindirectly includes data can be obtained.

Note that even if data with the same value is stored in memory cells,fluctuation in levels of the read potential Vdata occurs due tovariation in characteristics of the memory cells, so that the levels ofpotentials might be widely distributed. Thus, the level of the referencepotential Vref is determined in consideration of fluctuation in thepotential Vdata in order to read the value of data accurately.

Since FIG. 5 illustrates an example of a reading circuit at the timewhen a binary digital value is used, one operational amplifier used forreading data is used for one node to which the potential Vdata isapplied. However, the number of operational amplifiers is not limitedthereto. When n-valued data (n is a natural number of 2 or more) isused, the number of operational amplifiers used for one node to whichthe potential Vdata is applied is (n−1).

This embodiment can be implemented by being combined as appropriate withany of the above embodiments.

Embodiment 4

In this embodiment, a method for manufacturing a memory device will bedescribed by giving an example in which an oxide semiconductor is usedfor an active layer of a transistor 109 in a memory cell 100 and siliconis used for an active layer of a transistor included in a drivercircuit, illustrated in FIG. 2.

Besides silicon, a semiconductor material such as germanium, silicongermanium, or single crystal silicon carbide may be used for thetransistor included in the driver circuit. For example, the transistorincluding silicon can be formed using a single crystal semiconductorsubstrate such as a silicon wafer, a silicon thin film which is formedby an SOI method, a silicon thin film which is formed by a vapordeposition method, or the like. Alternatively, in an embodiment of thepresent invention, all of the transistors included in the memory cellsmay include an oxide semiconductor.

In this embodiment, first, as illustrated in FIG. 6A, an insulating film701 and a single crystal semiconductor film 702 are formed over asubstrate 700.

Although there is no particular limitation on a material which can beused as the substrate 700, it is necessary that the material have atleast heat resistance high enough to withstand heat treatment to beperformed later. For example, a glass substrate formed by a fusionprocess or a float process, a quartz substrate, a semiconductorsubstrate, a ceramic substrate, or the like can be used as the substrate700. In the case where the temperature of the heat treatment to beperformed later is high, a glass substrate whose strain point is greaterthan or equal to 730° C. is preferably used as the glass substrate.

In this embodiment, an example in which the semiconductor film 702 isformed using single crystal silicon is given as a method for forming thetransistor included in the driver circuit. Note that a specific exampleof a method for forming the single crystal semiconductor film 702 isbriefly described. First, an ion beam including ions which areaccelerated by an electric field enters a bond substrate which is thesingle crystal semiconductor substrate and an embrittlement layer whichis fragile because of local disorder of the crystal structure is formedin a region at a certain depth from a surface of the bond substrate. Thedepth at which the embrittlement layer is formed can be adjusted by theacceleration energy of the ion beam and the angle at which the ion beamenters. Then, the bond substrate and the substrate 700 which is providedwith the insulating film 701 are attached to each other so that theinsulating film 701 is provided therebetween. After the bond substrateand the substrate 700 overlap with each other, a pressure ofapproximately 1 N/cm² to 500 N/cm², preferably 11 N/cm² to 20 N/cm² isapplied to part of the bond substrate and part of the substrate 700 sothat the substrates are attached to each other. When the pressure isapplied, bonding between the bond substrate and the insulating film 701starts from the parts, which results in bonding of the entire surfacewhere the bond substrate and the insulating film 701 are in closecontact with each other. Subsequently, heat treatment is performed,whereby the microvoids that exist in the embrittlement layer arecoupled, so that a volume of microvoids are increased. Accordingly, asingle crystal semiconductor film which is part of the bond substrate isseparated from the bond substrate along the embrittlement layer. Theheat treatment is performed at a temperature not exceeding the strainpoint of the substrate 700. Then, the single crystal semiconductor filmis processed into a desired shape by etching or the like, so that thesemiconductor film 702 can be formed.

In order to control the threshold voltage, an impurity element impartingp-type conductivity, such as boron, aluminum, or gallium, or an impurityelement imparting n-type conductivity, such as phosphorus or arsenic,may be added to the semiconductor film 702. An impurity element forcontrolling the threshold voltage may be added to the semiconductor filmwhich is not patterned or may be added to the patterned semiconductorfilm 702. Alternatively, the impurity element for controlling thethreshold voltage may be added to the bond substrate. Alternatively, theimpurity element may be added to the bond substrate in order to roughlycontrol the threshold voltage, and the impurity element may be furtheradded to the semiconductor film which is not patterned or the patternedsemiconductor film 702 in order to finely control the threshold voltage.

Note that although an example in which a single crystal semiconductorfilm is used is described in this embodiment, the present invention isnot limited to this structure. For example, a polycrystalline,microcrystalline, or amorphous semiconductor film which is formed overthe insulating film 701 by a vapor deposition method may be used.Alternatively, the semiconductor film may be crystallized by a knowntechnique. As the known technique of crystallization, a lasercrystallization method using a laser beam and a crystallization methodusing a catalytic element are given. Alternatively, a crystallizationmethod using a catalytic element and a laser crystallization method maybe combined. When a heat-resistant substrate such as a quartz substrateis used, a crystallization method combined with a thermalcrystallization method using an electrically heated oven, a lampannealing crystallization method using infrared light, a crystallizationmethod using a catalytic element, or a high-temperature annealing methodat approximately 950° C., may be used.

Next, as illustrated in FIG. 6B, a gate insulating film 703 is formedover the semiconductor film 702. Then, a gate electrode 704 is formedover the gate insulating film 703.

The gate insulating film 703 can be formed by oxidation or nitriding ofa surface of the semiconductor film 702 by high-density plasmatreatment, heat treatment, or the like. The high-density plasmatreatment is performed, for example, by using a mixed gas of an inertgas such as He, Ar, Kr, or Xe, and oxygen, nitrogen oxide, ammonia,nitrogen, hydrogen, or the like. In this case, by exciting plasma byintroduction of microwaves, plasma with a low electron temperature andhigh density can be generated. By oxidation or nitriding of the surfaceof the semiconductor film with oxygen radicals (including OH radicals insome cases) or nitrogen radicals (including NH radicals in some cases)generated by such high-density plasma, an insulating film with athickness of 1 nm to 20 nm, preferably 5 nm to 10 nm can be formed so asto be in contact with the semiconductor film. For example, a surface ofthe semiconductor film 702 is oxidized or nitrided using nitrous oxide(N₂O) diluted with Ar by 1 times to 3 times (flow ratio) by applicationof a microwave (2.45 GHz) power of 3 kW to 5 kW at a pressure of 10 Pato 30 Pa. By this treatment, an insulating film having a thickness of 1nm to 10 nm (preferably 2 nm to 6 nm) is formed. Further, nitrous oxide(N₂O) and silane (SiH₄) are introduced and a microwave (2.45 GHz)electric power of 3 kW to 5 kW is applied with a pressure of 10 Pa to 30Pa so that a silicon oxynitride film is formed by a vapor depositionmethod, thereby forming the gate insulating film. With a combination ofa solid-phase reaction and a reaction by a vapor deposition method, thegate insulating film with low interface state density and excellentwithstand voltage can be formed.

The oxidation or nitriding of the semiconductor film by the high-densityplasma treatment proceeds by solid-phase reaction. Thus, interface statedensity between the gate insulating film 703 and the semiconductor film702 can be extremely low. Further, by direct oxidation or nitriding ofthe semiconductor film 702 by high-density plasma treatment, variationin the thickness of the insulating film to be formed can be suppressed.Moreover, in the case where the semiconductor film has crystallinity,the surface of the semiconductor film is oxidized with solid-phasereaction by the high-density plasma treatment to suppress fast oxidationonly in a crystal grain boundary; therefore, the gate insulating filmwith uniformity and low interface state density can be formed.Variations in the characteristics of a transistor whose gate insulatingfilm partly or entirely includes an insulating film formed byhigh-density plasma treatment can be suppressed.

The gate insulating film 703 may be formed using a single layer or astack of layers using a film including silicon oxide, silicon nitrideoxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminumoxide, tantalum oxide, yttrium oxide, hafnium silicate (HfSi_(x)O_(y),(x>0, y>0)), hafnium silicate (HfSi_(x)O_(y) (x>0, y>0)) to whichnitrogen is added, hafnium aluminate (HfAl_(x)O_(y), (x>0, y>0)) towhich nitrogen is added, or the like by a plasma CVD method, asputtering method, or the like.

Note that, in this specification, an oxynitride refers to a materialcontaining a larger amount of oxygen than that of nitrogen, and anitride oxide refers to a material containing a larger amount ofnitrogen than that of oxygen.

The thickness of the gate insulating film 703 can be, for example,greater than or equal to 1 nm and less than or equal to 100 nm,preferably greater than or equal to 10 nm and less than or equal to 50nm. In this embodiment, a single-layer insulating film containingsilicon oxynitride with a thickness of about 20 nm formed by a plasmaCVD method is used as the gate insulating film 703.

A conductive film is formed so as to cover the gate insulating film 703and then is processed (patterned) into a predetermined shape, so thatthe gate electrode 704 can be formed. The conductive film can be formedby a CVD method, a sputtering method, a vapor deposition method, a spincoating method, or the like. For the conductive film, tantalum (Ta),tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper(Cu), chromium (Cr), niobium (Nb), or the like can be used. An alloycontaining the above-described metal as a main component or a compoundcontaining the above-described metal may be used. Alternatively, theconductive film may be formed using a semiconductor such aspolycrystalline silicon doped with an impurity element such asphosphorus which imparts conductivity to the semiconductor film.

Note that the gate electrode 704 may be formed using a single-layerconductive film or a stacked-layer conductive film of a plurality offilms.

As a combination of two conductive films, tantalum nitride or tantalumcan be used for a first conductive film and tungsten can be used for asecond conductive film. Besides, the following combinations are given:tungsten nitride and tungsten, molybdenum nitride and molybdenum,aluminum and tantalum, aluminum and titanium, and the like. Sincetungsten and tantalum nitride have high heat resistance, a heattreatment aimed at thermal activation can be performed in subsequentsteps after forming the two conductive films. Alternatively, as thecombination of the two conductive films, for example, nickel silicideand silicon doped with an impurity element which imparts n-typeconductivity, tungsten silicide and silicon doped with an impurityelement which imparts n-type conductivity, or the like can be used.

In the case of using a three-layer structure which is stacked with morethan three conductive films, a stacked structure of a molybdenum film,an aluminum film, and a molybdenum film is preferable.

A light-transmitting oxide conductive film of indium oxide, a mixture ofindium oxide and tin oxide, a mixture of indium oxide and zinc oxide,zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, zinc galliumoxide, or the like can be used as the gate electrode 704.

In this embodiment, the gate electrode 704 in which tungsten with athickness of about 170 nm is stacked over tantalum nitride with athickness of about 30 nm is used.

Alternatively, the gate electrode 704 may be selectively formed by adroplet discharge method without the use of a mask. A droplet dischargemethod refers to a method for forming a predetermined pattern bydischarge or ejection of a droplet containing a predeterminedcomposition from an orifice, and includes an inkjet method in itscategory.

In addition, the gate electrode 704 may be formed by forming aconductive film, and the conductive film may be etched by inductivelycoupled plasma (ICP) etching under appropriately controlled conditions(e.g., the amount of electric power applied to a coiled electrode layer,the amount of electric power applied to an electrode layer on thesubstrate side, and the electrode temperature on the substrate side) tohave a desired tapered shape. In addition, angles and the like of thetapered shapes may also be controlled by a shape of a mask. Note that asan etching gas, a chlorine-based gas such as chlorine, boron chloride,silicon chloride, or carbon tetrachloride; a fluorine-based gas such ascarbon tetrafluoride, sulfur fluoride, or nitrogen fluoride; or oxygencan be used as appropriate.

Next, as illustrated in FIG. 6C, when an impurity element which impartone conductivity is added to the semiconductor film 702 with the gateelectrode 704 used as masks, a channel formation region 705 overlappingwith the gate electrode 704, and a pair of impurity regions 706 betweenwhich the channel formation region 705 is provided, are formed in thesemiconductor film 702.

In this embodiment, the case where an impurity element which impartsn-type conductivity (e.g., phosphorus) is added to the semiconductorfilm 702 is described.

Next, as illustrated in FIG. 6D, an insulating film 707, an insulatingfilm 708, and an insulating film 709 are formed to cover with the gateinsulating film 703 and the gate electrode 704. Specifically, aninorganic insulating film of silicon oxide, silicon nitride, siliconnitride oxide, silicon oxynitride, aluminum nitride, aluminum nitrideoxide, or the like can be used as the insulating film 707, theinsulating film 708, and the insulating film 709. The insulating film707, the insulating film 708, and the insulating film 709 areparticularly preferably formed using a low dielectric constant (low-k)material, so that capacitance due to an overlap of electrodes or wiringscan be sufficiently reduced. Note that a porous insulating filmincluding such a material may be employed as the insulating film 707,the insulating film 708, and the insulating film 709. Since the porousinsulating film has lower dielectric constant than a dense insulatinglayer, parasitic capacitance due to electrodes or wirings can be furtherreduced.

In this embodiment, an example in which a 50-nm-thick silicon oxynitridefilm is used for the insulating film 707, a 100-nm-thick silicon nitrideoxide film is used for the insulating film 708, and a 450-nm-thicksilicon oxynitride film is used as the insulating film 709 is described.In addition, although an example in which the insulating film 707, theinsulating film 708, and the insulating film 709 are formed over thegate electrode 704, is described in this embodiment, only one insulatingfilm or two insulating films may be formed over the gate electrode 704,or a plurality of insulating films of four or more layers may bestacked.

Next, as illustrated in FIG. 7A, an opening portion is formed in thegate insulating film 703, the insulating film 707, the insulating film708, and the insulating film 709 by etching or the like in order toexpose part of the impurity regions 706 and part of the gate electrode704; then, a conductive film 710 and a conductive film 711 which are incontact with the pair of the impurity regions 706, and a conductive film712 which is in contact with the gate electrode 704, are formed. Inaddition, an insulating film 713 is formed over the insulating film 709so as to cover the conductive films 710 to 712.

As the conductive film which serves as the conductive films 710 to 712,any of the following materials can be used: an element selected fromaluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten;an alloy including any of these elements; an alloy film including theabove elements in combination; and the like. Alternatively, a structuremay be employed in which a film of a refractory metal such as chromium,tantalum, titanium, molybdenum, or tungsten is stacked over or below ametal film of aluminum, copper, or the like. Aluminum or copper ispreferably used in combination with a refractory metal material in orderto avoid problems with heat resistance and corrosion. As the refractorymetal material, molybdenum, titanium, chromium, tantalum, tungsten,neodymium, scandium, yttrium, or the like can be used.

Further, the conductive film which serves as the conductive films 710 to712 may have a single-layer structure or a layered structure of two ormore layers. For example, a single-layer structure of an aluminum filmcontaining silicon, a two-layer structure in which a titanium film isstacked over an aluminum film, a three-layer structure in which atitanium film, an aluminum film, and a titanium film are stacked in thatorder, and the like can be given.

Further alternatively, for the conductive film serving as the conductivefilms 710 to 712, a conductive metal oxide may be used. As theconductive metal oxide, indium oxide, tin oxide, zinc oxide, a mixtureof indium oxide and tin oxide, a mixture of indium oxide and zinc oxide,or the conductive metal oxide material containing silicon or siliconoxide can be used.

In this embodiment, a conductive film in which a titanium film with athickness of about 50 nm, an aluminum film with a thickness of about 200nm, and a titanium film with a thickness of about 100 nm are stacked isused for the conductive films 710 to 712.

The insulating film 713 may have either a single layer structure or astacked layer of two layers or more, and preferably has a highly planarsurface. As the insulating film 713, silicon oxide, silicon nitride,silicon oxynitride, or silicon nitride oxide can be used, for exampleThe insulating film 713 can be formed by a CVD method such as a plasmaenhanced CVD method, a photo CVD method, or a thermal CVD method.

Further, as the insulating film 713, a silicon oxide film formed oforganosilane by chemical vapor deposition can be used. For organosilane,tetraethoxysilane (TEOS) (chemical formula: Si(OC₂H₅)₄), trimethylsilane(TMS) (chemical formula: (CH₃)₃SiH), tetramethylcyclotetrasiloxane(TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane(HMDS), triethoxysilane (chemical formula: SiH(OC₂H₅)₃),tris(dimethylamino)silane (chemical formula: SiH(N(CH₃)₂)₃), or the likecan be used. It is needless to say that silicon oxide, siliconoxynitride, silicon nitride, silicon nitride oxide, or the like may beformed using inorganic silane such as monosilane, disilane, ortrisilane.

In this embodiment, the insulating film 713 having a thickness of about1.5 μm and including silicon oxide is formed using TEOS.

Through the above process, a transistor 230 included in the drivercircuit can be formed. The transistor 230 includes the semiconductorfilm 702, the gate insulating film 703 provided over the semiconductorfilm 702, the gate electrode 704 formed to overlap with thesemiconductor film 702 over the gate insulating film 703, and theconductive film 710 and the conductive film 711 which function as asource electrode and a drain electrode and are connected to the impurityregion 706 included in the semiconductor film 702.

Next, as illustrated in FIG. 7B, the insulating film 713 is subjected toCMP (chemical mechanical polishing) or etching, so that surface of theconductive film 712 is exposed. Note that in order to improve thecharacteristics of the transistor 109 which is formed later, a surfaceof the insulating film 713 is preferably flattened as much as possible.

Next, a method for forming the transistor 109 is described. First, asillustrated in FIG. 7C, an oxide semiconductor film 715 is formed overthe insulating film 714 after an insulating film 714 is formed over theinsulating film 713 and the conductive film 712.

The insulating film 714 can be formed with the use of the same materialas the insulating film 707 to the insulating film 709. In thisembodiment, a silicon oxynitride film having a thickness of about 300 nmis used for the insulating film 714.

The oxide semiconductor film 715 can be formed by processing an oxidesemiconductor film formed over the insulating film 714 into a desiredshape. The thickness of the oxide semiconductor film is greater than orequal to 2 nm and less than or equal to 200 nm, preferably greater thanor equal to 3 nm and less than or equal to 50 nm, more preferablygreater than or equal to 3 nm and less than or equal to 20 nm. The oxidesemiconductor film is deposited by a sputtering method using an oxidesemiconductor target. Moreover, the oxide semiconductor film can beformed by a sputtering method in a rare gas (e.g., argon) atmosphere, anoxygen atmosphere, or a mixed atmosphere of a rare gas (e.g., argon) andoxygen.

Note that before the oxide semiconductor film is deposited by asputtering method, dust attached to the surface of the insulating film714 is preferably removed by reverse sputtering in which an argon gas isintroduced and plasma is generated. The reverse sputtering refers to amethod in which, without application of voltage to a target side, an RFpower source is used for application of voltage to a substrate side inan argon atmosphere to generate plasma in the vicinity of the substrateto modify a surface. Note that instead of an argon atmosphere, anitrogen atmosphere, a helium atmosphere, or the like may be used.Alternatively, an argon atmosphere to which oxygen, nitrous oxide, orthe like is added may be used. Alternatively, an argon atmosphere towhich chlorine, carbon tetrafluoride, or the like is added may be used.

As the oxide semiconductor, for example, an indium oxide, a tin oxide, azinc oxide, a two-component metal oxide such as an In—Zn-based oxide, aSn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, aSn—Mg-based oxide, an In—Mg-based oxide, or an In—Ga-based oxide, athree-component metal oxide such as an In—Ga—Zn-based oxide (alsoreferred to as IGZO), an In—Al—Zn-based oxide, an In—Sn—Zn-based oxide,a Sn—Ga—Zn-based oxide, an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide,an In—Hf—Zn-based oxide, an In—La—Zn-based oxide, an In—Ce—Zn-basedoxide, an In—Pr—Zn-based oxide, an In—Nd—Zn-based oxide, anIn—Sm—Zn-based oxide, an In—Eu—Zn-based oxide, an In—Gd—Zn-based oxide,an In—Tb—Zn-based oxide, an In—Dy—Zn-based oxide, an In—Ho—Zn-basedoxide, an In—Er—Zn-based oxide, an In—Tm—Zn-based oxide, anIn—Yb—Zn-based oxide, or an In—Lu—Zn-based oxide, a four-component metaloxide such as an In—Sn—Ga—Zn-based oxide, an In—Hf—Ga—Zn-based oxide, anIn—Al—Ga—Zn-based oxide, an In—Sn—Al—Zn-based oxide, anIn—Sn—Hf—Zn-based oxide, or an In—Hf—Al—Zn-based oxide can be used. Theabove oxide semiconductor may include silicon.

In this embodiment, as the oxide semiconductor film, an In—Ga—Zn-basedoxide semiconductor thin film with a thickness of 30 nm, which isobtained by a sputtering method using a target including indium (In),gallium (Ga), and zinc (Zn), is used. As the above target, it ispreferable to use a target having an atomic ratio of In:Ga:Zn=1:1:1,4:2:3, 3:1:2, 1:1:2, 2:1:3, or 3:1:4. The filling rate of the targetincluding In, Ga, and Zn is 90% or higher and 100% or lower, andpreferably 95% or higher and lower than 100%. With the use of the targetwith high filling rate, a dense oxide semiconductor film is formed.

Note that in the case where an In—Zn-based material is used as an oxidesemiconductor film, a target to be used has a composition ratio ofIn:Zn=50:1 to 1:2 in an atomic ratio (In₂O₃:ZnO=25:1 to 1:4 in a molarratio), preferably In:Zn=20:1 to 1:1 in an atomic ratio (In₂O₃:ZnO=10:1to 1:2 in a molar ratio), further preferably In:Zn=1.5:1 to 15:1 in anatomic ratio (In₂O₃:ZnO=3:4 to 15:2 in a molar ratio). For example, whenan atomic ratio of In:Zn:O=X:Y:Z in a target used for formation of anIn—Zn-based oxide semiconductor, the relation Z>1.5X+Y is satisfied. Themobility can be improved by keeping the ratio of Zn within the aboverange.

In the case of forming a film of an In—Sn—Zn-based oxide semiconductorfilm as an oxide semiconductor film by a sputtering method, it ispreferable to use an In—Sn—Zn—O target having an atomic ratio ofIn:Sn:Zn=1:1:1, 2:1:3, 1:2:2, or 20:45:35.

In this embodiment, the oxide semiconductor film is deposited in such amanner that the substrate is held in a treatment chamber kept in areduced pressure state, moisture remaining in the treatment chamber isremoved, a sputtering gas from which hydrogen and moisture are removedis introduced, and the target is used. The substrate temperature may behigher than or equal to 100° C. and lower than or equal to 600° C.,preferably higher than or equal to 200° C. and lower than or equal to400° C. at the deposition. By depositing the oxide semiconductor film ina state where the substrate is heated, the concentration of impuritiesincluded in the deposited oxide semiconductor film can be reduced. Inaddition, damage by sputtering can be reduced. In order to removeremaining moisture in the treatment chamber, an entrapment vacuum pumpis preferably used. For example, a cryopump, an ion pump, or a titaniumsublimation pump is preferably used. The evacuation unit may be a turbopump provided with a cold trap. In the treatment chamber which isevacuated with the cryopump, for example, a hydrogen atom, a compoundcontaining a hydrogen atom, such as water (H₂O), (more preferably, alsoa compound containing a carbon atom), and the like are removed, wherebythe impurity concentration in the oxide semiconductor film deposited inthe treatment chamber can be reduced.

As one example of the deposition condition, the distance between thesubstrate and the target is 100 mm, the pressure is 0.6 Pa, thedirect-current (DC) power is 0.5 kW, and the atmosphere is an oxygenatmosphere (the proportion of the oxygen flow rate is 100%). Note that apulsed direct-current (DC) power supply is preferable because dustgenerated in deposition can be reduced and the film thickness can bemade uniform.

Moreover, when the leakage rate of the treatment chamber of thesputtering apparatus is set to lower than or equal to 1×10⁻¹⁰Pa·m³/second, entry of impurities such as an alkali metal or hydrideinto the oxide semiconductor film that is being formed by a sputteringmethod can be reduced. Further, with the use of an entrapment vacuumpump as an exhaustion system, counter flow of impurities, such as alkalimetal, hydrogen atoms, hydrogen molecules, water, a hydroxyl group, orhydride, from the exhaustion system can be reduced.

When the purity of the target is set to 99.99% or higher, alkali metal,hydrogen atoms, hydrogen molecules, water, a hydroxyl group, hydride, orthe like mixed to the oxide semiconductor film can be reduced. Inaddition, when the target is used, the concentration of alkali metalsuch as lithium, sodium, or potassium can be reduced in the oxidesemiconductor film.

Note that in order that hydrogen, a hydroxyl group, and moisture becontained in the oxide semiconductor film as little as possible, it ispreferable that an impurity such as hydrogen or moisture that isadsorbed on the substrate 700 be eliminated and exhausted by preheatingof the substrate 700 over which the insulating film 714 are formed in apreheating chamber of a sputtering apparatus, as pretreatment fordeposition. The temperature for the preheating is higher than or equalto 100° C. and lower than or equal to 400° C., preferably higher than orequal to 150° C. and lower than or equal to 300° C. As an evacuationmeans, a cryopump is preferably provided in the preheating chamber. Notethat this preheating treatment can be omitted. This preheating may besimilarly performed on the substrate 700 over which conductive films716, 717, and 718 are formed before the deposition of a gate insulatingfilm 719.

Note that etching for forming the oxide semiconductor film 715 may bedry etching, wet etching, or both dry etching and wet etching. As anetching gas used for dry etching, a gas containing chlorine (achlorine-based gas such as chlorine (Cl₂), boron trichloride (BC₃),silicon tetrachloride (SiCl₄), or carbon tetrachloride (CCl₄)) ispreferably used. Alternatively, a gas containing fluorine (afluorine-based gas such as carbon tetrafluoride (CF₄), sulfurhexafluoride (SF₆), nitrogen trifluoride (NF₃), or trifluoromethane(CHF₃)), hydrogen bromide (HBr), oxygen (O₂), any of these gases towhich a rare gas such as helium (He) or argon (Ar) is added, or the likecan be used.

As the dry etching method, a parallel plate RIE (reactive ion etching)method or an ICP (inductively coupled plasma) etching method can beused. In order to etch the film to have a desired shape, the etchingconditions (e.g., the amount of electric power applied to a coiledelectrode, the amount of electric power applied to an electrode on thesubstrate side, and the electrode temperature on the substrate side) areadjusted as appropriate.

As an etchant used for the wet etching, a mixed solution of phosphoricacid, acetic acid, and nitric acid, or organic acid such as citric acidor oxalic acid can be used. In this embodiment, ITO-07N (produced byKANTO CHEMICAL CO., INC.) is used.

A resist mask used for forming the oxide semiconductor film 715 may beformed by an inkjet method. Formation of the resist mask by an inkjetmethod needs no photomask; thus, manufacturing cost can be reduced.

Note that it is preferable that reverse sputtering be performed beforethe formation of a conductive film in a subsequent step so that a resistresidue and the like that attaches onto surfaces of the oxidesemiconductor film 715 and the insulating film 714 are removed.

Note that the oxide semiconductor film deposited by sputtering or thelike contains a large amount of moisture or hydrogen (including ahydroxyl group) as an impurity in some cases. Moisture or hydrogeneasily forms donor levels and thus serves as an impurity in the oxidesemiconductor. In an embodiment of the present invention, in order toreduce impurities such as moisture or hydrogen in the oxidesemiconductor film (dehydration or dehydrogenation), the oxidesemiconductor film 715 is preferably subjected to heat treatment in areduced pressure atmosphere, an inert gas atmosphere of nitrogen, a raregas, or the like, an oxygen gas atmosphere, or an ultra dry airatmosphere (the moisture amount is 20 ppm (−55° C. by conversion into adew point) or less, preferably 1 ppm or less, further preferably 10 ppbor less, in the case where the measurement is performed by a dew pointmeter in a cavity ring down laser spectroscopy (CRDS) system).

By subjection the oxide semiconductor film 715 to heat treatment,moisture or hydrogen in the oxide semiconductor film 715 can beeliminated. Specifically, heat treatment may be performed at atemperature higher than or equal to 250° C. and lower than or equal to750° C., preferably higher than or equal to 400° C. and lower than thestrain point of a substrate. For example, heat treatment may beperformed at 500° C. for approximately three minutes to six minutes.When RTA is used for the heat treatment, dehydration or dehydrogenationcan be performed in a short time; thus, treatment can be performed evenat a temperature higher than the strain point of a glass substrate.

In this embodiment, an electrical furnace that is one of heat treatmentapparatuses is used.

Note that the heat treatment apparatus is not limited to an electricfurnace, and may have a device for heating an object by heat conductionor heat radiation from a heating element such as a resistance heatingelement. For example, an RTA (rapid thermal anneal) apparatus such as aGRTA (gas rapid thermal anneal) apparatus or an LRTA (lamp rapid thermalanneal) apparatus can be used. An LRTA apparatus is an apparatus forheating an object to be processed by radiation of light (anelectromagnetic wave) emitted from a lamp such as a halogen lamp, ametal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressuresodium lamp, or a high pressure mercury lamp. A GRTA apparatus is anapparatus for heat treatment using a high-temperature gas. As the gas,an inert gas which does not react with an object to be processed by heattreatment, like nitrogen or a rare gas such as argon is used.

In the heat treatment, it is preferable that moisture, hydrogen, and thelike be not contained in nitrogen or a rare gas such as helium, neon, orargon. Alternatively, the purity of nitrogen or a rare gas such ashelium, neon, or argon which is introduced into the heat treatmentapparatus is preferably greater than or equal to 6 N (99.9999%), morepreferably greater than or equal to 7 N (99.99999%) (i.e., the impurityconcentration is less than or equal to 1 ppm, preferably less than orequal to 0.1 ppm).

Note that it has been pointed out that an oxide semiconductor isinsensitive to impurities, there is no problem when a considerableamount of metal impurities is contained in the film, and therefore,soda-lime glass which contains a large amount of alkali metal such assodium and is inexpensive can also be used (Kamiya, Nomura, and Hosono,“Engineering application of solid state physics: Carrier transportproperties and electronic structures of amorphous oxide semiconductors:the present status”, KOTAI BUTSURI (SOLID STATE PHYSICS), 2009, Vol. 44,pp. 621-633). But such consideration is not appropriate. Alkali metal isnot an element included in an oxide semiconductor, and therefore, is animpurity. Also, alkaline earth metal is impurity in the case wherealkaline earth metal is not an element included in an oxidesemiconductor. Alkali metal, in particular, Na becomes Na⁺ when aninsulating film in contact with the oxide semiconductor film is an oxideand Na diffuses into the insulating layer. In addition, in the oxidesemiconductor film, Na cuts or enters a bond between metal and oxygenwhich are included in an oxide semiconductor. As a result, for example,deterioration of characteristics of the transistor, such as anormally-on state of the transistor due to shift of a threshold voltagein the negative direction, or a reduction in mobility, occurs. Inaddition, variation in characteristics also occurs. Such deteriorationof characteristics of the transistor and variation in characteristicsdue to the impurity remarkably appear when the hydrogen concentration inthe oxide semiconductor film is very low. Therefore, when the hydrogenconcentration in the oxide semiconductor film is less than or equal to1×10¹⁸ /cm³, preferably less than or equal to 1×10¹⁷/cm³, theconcentration of the above impurity is preferably reduced. Specifically,a measurement value of a Na concentration by secondary ion massspectrometry is preferably less than or equal to 5×10¹⁶/cm³, morepreferably less than or equal to 1×10¹⁶/cm³, still more preferably lessthan or equal to 1×10¹⁵/cm³. In a similar manner, a measurement value ofa Li concentration is preferably less than or equal to 5×10¹⁵/cm³, morepreferably less than or equal to 1×10¹⁵/cm³. In a similar manner, ameasurement value of a K concentration is preferably less than or equalto 5×10¹⁵/cm³, more preferably less than or equal to 1×10¹⁵/cm³.

Through the above process, the concentration of hydrogen in the oxidesemiconductor film 715 can be reduced and the oxide semiconductor film715 can be highly purified. Thus, the oxide semiconductor film can bestabilized. In addition, heat treatment at a temperature of lower thanor equal to the glass transition temperature makes it possible to forman oxide semiconductor film with a wide band gap in which carrierdensity is extremely low. Therefore, the transistor can be manufacturedusing a large-sized substrate, so that the productivity can beincreased. In addition, by using the oxide semiconductor film in whichthe hydrogen concentration is reduced and the purity is improved, it ispossible to manufacture a transistor with high withstand voltage and anextremely low off-state current. The above heat treatment can beperformed at any time after the oxide semiconductor film is formed.

Note that the oxide semiconductor film may be amorphous or may havecrystallinity. As an oxide semiconductor film having crystallinity, aCAAC-OS film (c axis aligned crystal oxide semiconductor film) includinga crystal with c-axis orientation (also referred to as CAAC) is alsopreferable because the effect of improving the reliability of atransistor can be obtained.

Sputtering may be performed to form an oxide semiconductor filmincluding a CAAC-OS film. In order to obtain a CAAC-OS film bysputtering, it is important to form hexagonal crystals in an initialstage of deposition of an oxide semiconductor film and to cause crystalgrowth from the hexagonal crystals as cores. In order to achieve this,it is preferable that the distance between the target and the substratebe made to be longer (e.g., 150 mm to 200 mm) and a substrate heatingtemperature be 100° C. to 500° C., more preferably 200° C. to 400° C.,still preferably 250° C. to 300° C. In addition to this, the depositedoxide semiconductor film is subjected to heat treatment at a temperaturehigher than the substrate heating temperature in the deposition.Therefore, micro-defects in the film and defects at the interface of astacked layer can be compensated.

The CAAC-OS film is not completely single crystal nor completelyamorphous. The CAAC-OS film is an oxide semiconductor film with acrystal-amorphous mixed phase structure where crystal parts are includedin an amorphous phase. Note that in most cases, the crystal part fitsinside a cube whose one side is less than 100 nm. From an observationimage obtained with a transmission electron microscope (TEM), a boundarybetween an amorphous part and a crystal part in the CAAC-OS film is notclear. Further, with the TEM, a grain boundary in the CAAC-OS film isnot found. Thus, in the CAAC-OS film, a reduction in electron mobility,due to the grain boundary, is suppressed.

In each of the crystal parts included in the CAAC-OS film, a c-axis isaligned in a direction parallel to a normal vector of a surface wherethe CAAC-OS film is formed or a normal vector of a surface of theCAAC-OS film, triangular or hexagonal atomic arrangement when seen fromthe direction perpendicular to the a-b plane is formed, and metal atomsare arranged in a layered manner or metal atoms and oxygen atoms arearranged in a layered manner when seen from the direction perpendicularto the c-axis. Note that, among crystal parts, the directions of thea-axis and the b-axis of one crystal part may be different from those ofanother crystal part. In this specification, a simple term“perpendicular” includes a range from 85° to 95°. In addition, a simpleterm “parallel” includes a range from −5° to 5°.

In the CAAC-OS film, distribution of crystal parts is not necessarilyuniform. For example, in the formation process of the CAAC-OS film, inthe case where crystal growth occurs from a surface side of the oxidesemiconductor film, the proportion of crystal parts in the vicinity ofthe surface of the CAAC-OS film is higher than that in the vicinity ofthe surface where the CAAC-OS film is formed in some cases.

Since the c-axes of the crystal parts included in the CAAC-OS film arealigned in the direction parallel to a normal vector of a surface wherethe CAAC-OS film is formed or a normal vector of a surface of theCAAC-OS film, the directions of the c-axes may be different from eachother depending on the shape of the CAAC-OS film (the cross-sectionalshape of the surface where the CAAC-OS film is formed or thecross-sectional shape of the surface of the CAAC-OS film). Note thatwhen the CAAC-OS film is formed, the direction of c-axis of the crystalpart is the direction parallel to a normal direction (vector) of thesurface where the CAAC-OS film is formed or a normal direction (vector)of the surface of the CAAC-OS film. The crystal part is formed by filmformation or by performing treatment for crystallization such as heattreatment after film formation.

With use of the CAAC-OS film in a transistor, change in electriccharacteristics of the transistor due to irradiation with visible lightor ultraviolet light can be reduced. Thus, the transistor has highreliability.

Next as illustrated in FIG. 8A, part of the conductive film 710 isexposed by formation of an opening by etching or the like in theinsulating film 713 and the insulating film 714, and then the conductivefilm 716 in contact with the conductive film 710 in the opening, and theconductive film 717 and the conductive film 718 in contact with theoxide semiconductor film 715 are formed. The conductive film 717 and theconductive film 718 function as a source and drain electrodes.

Specifically, the conductive films 716, 717, and 718 can be formed asfollows: a conductive film is formed over the insulating film 714 bysputtering or vacuum evaporation so as to cover the opening, and then,the conductive film is processed (patterned) into the predeterminedshape.

As the conductive film which serves as the conductive films 716, 717,and 718, any of the following materials can be used: an element selectedfrom aluminum, chromium, copper, tantalum, titanium, molybdenum, ortungsten; an alloy including any of these elements; an alloy filmincluding the above elements in combination; and the like.Alternatively, a structure may be employed in which a film of arefractory metal such as chromium, tantalum, titanium, molybdenum, ortungsten is stacked over or below a metal film of aluminum, copper, orthe like. Aluminum or copper is preferably used in combination with arefractory metal material in order to avoid problems with heatresistance and corrosion. As the refractory metal material, molybdenum,titanium, chromium, tantalum, tungsten, neodymium, scandium, yttrium, orthe like can be used.

Further, the conductive film which serves as the conductive films 716,717, and 718 may have a single-layer structure or a layered structure oftwo or more layers. For example, a single-layer structure of an aluminumfilm containing silicon, a two-layer structure in which a titanium filmis stacked over an aluminum film, a three-layer structure in which atitanium film, an aluminum film, and a titanium film are stacked in thatorder, and the like can be given. A Cu—Mg—Al alloy, a Mo—Ti alloy, Ti,and Mo have high adhesiveness with an oxide film. Therefore, for theconductive films 716, 717, and 718, a layered structure is employed inwhich a conductive film including a Cu—Mg—Al alloy, a Mo—Ti alloy, Ti,or Mo is used for the lower layer and a conductive film including Cu isused for the upper layer; thus, the adhesiveness between an insulatingfilm 714 which is an oxide film and the conductive films 716, 717, and718 can be increased.

For the conductive film which serves as the conductive films 716, 717,and 718, a conductive metal oxide may be used. As the conductive metaloxide, indium oxide, tin oxide, zinc oxide, a mixture of indium oxideand tin oxide, a mixture of indium oxide and zinc oxide, or theconductive metal oxide material containing silicon or silicon oxide canbe used.

In the case where heat treatment is performed after formation of theconductive film, the conductive film preferably has heat resistanceenough to withstand the heat treatment.

In this embodiment, each of the conductive films 716, 717, and 718 is a150-nm-thick tungsten film.

Note that each material and etching conditions are adjusted asappropriate so that the oxide semiconductor film 715 is not removed asmuch as possible at the time of etching the conductive film. Dependingon the etching conditions, an exposed portion of the oxide semiconductorfilm 715 is partly etched, so that a groove (a depression portion) isformed in some cases.

In this embodiment, a tungsten film is used for the conductive films716, 717, and 718. Therefore, wet etching can be selectively performedon the conductive film using a solution (an ammonia hydrogen peroxidemixture) containing ammonia and hydrogen peroxide water. As the ammoniahydrogen peroxide mixture, specifically, a solution in which hydrogenperoxide water of 31 wt %, ammonia water of 28 wt %, and water are mixedat a volume ratio of 5:2:2 is used.

Alternatively, dry etching may be performed on the conductive film withthe use of a gas containing tetrafluoride (CF₄), chlorine (Cl₂), oxygen,or the like.

In order to reduce the number of photomasks and steps in aphotolithography step, etching may be performed with the use of a resistmask formed using a multi-tone mask which is a light-exposure maskthrough which light is transmitted so as to have a plurality ofintensities. A resist mask formed using a multi-tone mask has aplurality of thicknesses and can be changed in shape by etching; thus,the resist mask can be used in a plurality of etching processes forprocessing films into different patterns. Therefore, a resist maskcorresponding to at least two kinds or more of different patterns can beformed by one multi-tone mask. Thus, the number of light-exposure maskscan be reduced and the number of corresponding photolithography stepscan be also reduced, whereby simplification of a process can berealized.

Further, an oxide conductive film functioning as a source region and adrain region may be provided between the oxide semiconductor film 715and the conductive films 717 and 718 functioning as source and drainelectrodes. The material of the oxide conductive film preferablycontains zinc oxide as a component and preferably does not containindium oxide. For such an oxide conductive film, zinc oxide, zincaluminum oxide, zinc aluminum oxynitride, gallium zinc oxide, or thelike can be used.

For example, in the case where the oxide conductive film is formed,patterning for forming the oxide conductive film and patterning forforming the conductive films 717 and 718 may be performed concurrently.

With provision of the oxide conductive film functioning as a sourceregion and a drain region, resistance between the oxide semiconductorfilm 715 and the conductive films 717 and 718 can be lowered, so thatthe transistor can operate at high speed. In addition, with provision ofthe oxide conductive film functioning as a source region and a drainregion, the withstand voltage of the transistor can be increased.

Next, plasma treatment may be performed using a gas such as N₂O, N₂, orAr. By this plasma treatment, water or the like adhering to an exposedsurface of the oxide semiconductor film is removed. Plasma treatment maybe performed using a mixture gas of oxygen and argon as well.

After the plasma treatment, as illustrated in FIG. 8B, the gateinsulating film 719 is formed so as to cover the conductive films 716,717, and 718 and the oxide semiconductor film 715. Then, a gateelectrode 720 is formed over the gate insulating film 719 so as tooverlap with the oxide semiconductor film 715, and a conductive film 721is formed over the conductive film 719 so as to overlap with theconductive film 717.

The gate insulating film 719 can be formed using a material and alayered structure which are similar to those of the gate insulating film703. Note that the gate insulating film 719 preferably includesimpurities such as moisture or hydrogen as little as possible, and thegate insulating film 719 may be formed using a single-layer insulatingfilm or a plurality of insulating films stacked. When hydrogen iscontained in the gate insulating film 719, hydrogen enters the oxidesemiconductor film 715 or oxygen in the oxide semiconductor film 715 isextracted by hydrogen, whereby the oxide semiconductor film 715 haslower resistance (n-type conductivity); thus, a parasitic channel mightbe formed. Thus, it is important that a deposition method in whichhydrogen is not used be employed in order to form the gate insulatingfilm 719 containing hydrogen as little as possible. A material having ahigh barrier property is preferably used for the gate insulating film719. As the insulating film having a high barrier property, a siliconnitride film, a silicon nitride oxide film, an aluminum nitride film, analuminum nitride oxide film, or the like can be used, for example. Whena plurality of insulating films stacked are used, an insulating filmhaving low proportion of nitrogen such as a silicon oxide film or asilicon oxynitride film is formed on a side which is closer to the oxidesemiconductor film 715 than the insulating film having a high barrierproperty. Then, the insulating film having a high barrier property isformed so as to overlap with the conductive films 716, 717, and 718 andthe oxide semiconductor film 715 with the insulating film having lowproportion of nitrogen sandwiched therebetween. When the insulating filmhaving a high barrier property is used, impurities such as moisture orhydrogen can be prevented from entering the oxide semiconductor film715, the gate insulating film 719, or the interface between the oxidesemiconductor film 715 and another insulating film and the vicinitythereof. In addition, the insulating film having low proportion ofnitrogen, such as a silicon oxide film or a silicon oxynitride film, isformed so as to be in contact with the oxide semiconductor film 715, sothat the insulating film having a high barrier property can be preventedfrom being in direct contact with the oxide semiconductor film 715.

In this embodiment, a silicon nitride film with a thickness of 30 nmwhich is formed by a sputtering method is used as the gate insulatingfilm 719. The substrate temperature at deposition may be higher than orequal to room temperature and lower than or equal to 400° C. and in thisembodiment, is 300° C.

After the gate insulating film 719 is formed, heat treatment may beperformed. The heat treatment is performed in a nitrogen atmosphere,ultra-dry air, or a rare gas (e.g., argon or helium) atmospherepreferably at a temperature higher than or equal to 200° C. and lowerthan or equal to 400° C., for example, higher than or equal to 250° C.and lower than or equal to 350° C. It is preferable that the watercontent in the gas be 20 ppm or less, preferably 1 ppm or less, furtherpreferably 10 ppb or less. In this embodiment, for example, heattreatment is performed at 250° C. in a nitrogen atmosphere for 1 hour.Alternatively, RTA treatment for a short time at a high temperature maybe performed before the formation of the conductive films 716, 717, and718 in a manner similar to that of the heat treatment performed on theoxide semiconductor film for reduction of moisture or hydrogen. Evenwhen oxygen defects are generated in the oxide semiconductor film 715 bythe heat treatment performed on the oxide semiconductor film 715 byperforming heat treatment after provision of the gate insulating film719 containing oxygen, oxygen is supplied to the oxide semiconductorfilm 715 from the gate insulating film 719. By the supply of oxygen tothe oxide semiconductor film 715, oxygen defects that serve as donorscan be reduced in the oxide semiconductor film 715 and thestoichiometric composition can be satisfied. As a result, the oxidesemiconductor film 715 can be substantially intrinsic and variation inelectrical characteristics of the transistor due to oxygen defects canbe reduced; thus, electrical characteristics can be improved. The timingof this heat treatment is not particularly limited as long as it isafter the formation of the gate insulating film 719. When this heattreatment serves as heat treatment in another step (e.g., heat treatmentat the time of formation of a resin film or heat treatment for loweringthe resistance of a transparent conductive film), the oxidesemiconductor film 715 can be made to be substantially intrinsic withoutthe increase in the number of steps.

Alternatively, the oxygen defects that serve as donors in the oxidesemiconductor film 715 may be reduced by subjecting the oxidesemiconductor film 715 to heat treatment in an oxygen atmosphere so thatoxygen is added to the oxide semiconductor. The heat treatment isperformed, for example, at a temperature higher than or equal to 100° C.and lower than 350° C., preferably higher than or equal to 150° C. andlower than 250° C. It is preferable that an oxygen gas used for the heattreatment under an oxygen atmosphere do not include water, hydrogen, orthe like. Alternatively, the purity of the oxygen gas which isintroduced into the heat treatment apparatus is preferably greater thanor equal to 6N (99.9999%) or more, further preferably greater than orequal to 7N (99.99999%) (that is, the impurity concentration in theoxygen gas is less than or equal to 1 ppm, preferably less than or equalto 0.1 ppm).

Alternatively, oxygen may be added to the oxide semiconductor film 715by an ion implantation method, an ion doping method, or the like so thatoxygen defects that serve as donors are reduced. For example, oxygenmade to be plasma with a microwave of 2.45 GHz may be added to the oxidesemiconductor film 715.

The gate electrode 720 and the conductive film 721 can be formed in sucha manner that a conductive film is formed over the gate insulating film719 and then is patterned. The gate electrode 720 and the conductivefilm 721 can be formed using a material and a layered structure whichare similar to those of the gate electrode 704 and the conductive films716, 717, and 718.

The thickness of each of the gate electrode 720 and the conductive film721 is 10 nm to 400 nm, preferably 100 nm to 300 nm. In this embodiment,after a conductive film with a thickness of 150 nm for the gateelectrode is formed by a sputtering method using a tungsten target, theconductive film is processed (patterned) into a desired shape byetching, whereby the gate electrode 720 and the conductive film 721 areformed. Note that a resist mask may be formed by an inkjet method.Formation of the resist mask by an inkjet method needs no photomask;thus, manufacturing cost can be reduced.

Through the above steps, the transistor 109 is formed.

Note that a portion where the conductive film 717 and the conductivefilm 721 overlap with each other with the gate insulating film 719provided therebetween corresponds to the capacitor 110.

In this embodiment, an example of the parallel plate capacitor 110 isshown but a stacked capacitor may be used in the memory device accordingto an embodiment of the present invention.

Although the transistor 109 is described as a single-gate transistor, amulti-gate transistor including a plurality of channel formation regionscan be formed when a plurality of gate electrodes which are electricallyconnected are included when needed.

Note that an insulating film which is in contact with the oxidesemiconductor film 715 (in this embodiment, corresponding to theinsulating film 714 and the gate insulating film 719) may be formedusing an insulating material containing an element that belongs to Group13 and oxygen. Many oxide semiconductor materials contain an elementthat belongs to Group 13, and an insulating material containing anelement that belongs to Group 13 works well with an oxide semiconductor.By using such an insulating material containing an element that belongsto Group 13 for the insulating film which is in contact with the oxidesemiconductor film, the state of an interface with the oxidesemiconductor film can be kept well.

An insulating material containing a Group 13 element refers to aninsulating material containing one or more elements that belong to Group13. As the insulating material containing a Group 13 element, a galliumoxide, an aluminum oxide, an aluminum gallium oxide, a gallium aluminumoxide, and the like are given. Here, aluminum gallium oxide refers to amaterial in which the amount of aluminum is larger than that of galliumin atomic percent, and gallium aluminum oxide refers to a material inwhich the amount of gallium is larger than or equal to that of aluminumin atomic percent.

For example, in the case of forming an insulating film in contact withan oxide semiconductor film containing gallium, a material includinggallium oxide may be used as an insulating film, so that favorablecharacteristics can be kept at the interface between the oxidesemiconductor film and the insulating film. When the oxide semiconductorfilm and the insulating film containing gallium oxide are provided incontact with each other, pileup of hydrogen at the interface between theoxide semiconductor film and the insulating film can be reduced, forexample. Note that a similar effect can be obtained in the case where anelement in the same group as a constituent element of the oxidesemiconductor is used in an insulating film. For example, it iseffective to form an insulating film with the use of a materialincluding aluminum oxide. Note that aluminum oxide has a property of noteasily transmitting water. Thus, it is preferable to use a materialincluding aluminum oxide in terms of preventing entry of water to theoxide semiconductor film.

The insulating film which is in contact with the oxide semiconductorfilm 715 preferably contains oxygen in a proportion higher than that inthe stoichiometric composition, by heat treatment in an oxygenatmosphere or oxygen doping. “Oxygen doping” refers to addition ofoxygen into a bulk. Note that the term “bulk” is used in order toclarify that oxygen is added not only to a surface of a thin film butalso to the inside of the thin film. In addition, “oxygen doping”includes “oxygen plasma doping” in which oxygen which is made to beplasma is added to a bulk. The oxygen doping may be performed by ionimplantation or ion doping.

For example, in the case where the insulating film which is in contactwith the oxide semiconductor film 715 is formed using gallium oxide, thecomposition of gallium oxide can be set to be Ga₂O_(X) (X=3+α, 0<α<1) byheat treatment in an oxygen atmosphere or oxygen doping.

In the case where the insulating film which is in contact with the oxidesemiconductor film 715 is formed using aluminum oxide, the compositionof aluminum oxide can be set to be Al₂O_(X) (X=3+α, 0<α<1) by heattreatment in an oxygen atmosphere or oxygen doping.

In the case where the insulating film which is in contact with the oxidesemiconductor film 715 is formed using gallium aluminum oxide (aluminumgallium oxide), the composition of gallium aluminum oxide (aluminumgallium oxide) can be set to be Ga_(X)Al_(2−X)O_(3+α) (0<X<2, 0<α<1) byheat treatment in an oxygen atmosphere or oxygen doping.

By oxygen doping, an insulating film which includes a region where theproportion of oxygen is higher than that in the stoichiometriccomposition can be formed. When the insulating film including such aregion is in contact with the oxide semiconductor film, oxygen thatexists excessively in the insulating film is supplied to the oxidesemiconductor film, and oxygen deficiency in the oxide semiconductorfilm or at the interface between the oxide semiconductor film and theinsulating film is reduced. Thus, the oxide semiconductor film can beformed to an intrinsic or substantially intrinsic oxide semiconductor.

The insulating film including a region where the proportion of oxygen ishigher than that in the stoichiometric composition may be applied toeither the insulating film placed on an upper side of the oxidesemiconductor film or the insulating film placed on a lower side of theoxide semiconductor film of the insulating films which are in contactwith the oxide semiconductor film 715; however, it is preferable toapply such an insulating film to both the insulating films which are incontact with the oxide semiconductor film 715. The above effect can beenhanced with a structure where the oxide semiconductor film 715 isprovided between the insulating films each including a region where theproportion of oxygen is higher than that in the stoichiometriccomposition, which are used as the insulating films in contact with theoxide semiconductor film 715 and positioned on the upper side and thelower side of the oxide semiconductor film 715.

The insulating films on the upper side and the lower side of the oxidesemiconductor film 715 may contain the same constituent element ordifferent constituent elements. For example, the insulating films on theupper side and the lower side may be both formed of gallium oxide whosecomposition is Ga₂O_(x) (x=3+α, 0<α<1). Alternatively, one of theinsulating films on the upper side and the lower side may be formed ofGa₂O_(x) (x=3+α, 0<α<1) and the other may be formed of aluminum oxidewhose composition is Al₂O_(x) (x=3+α, 0<α<1).

The insulating film which is in contact with the oxide semiconductorfilm 715 may be formed by a stack of insulating films each including aregion where the proportion of oxygen is higher than that in thestoichiometric composition. For example, the insulating film on theupper side of the oxide semiconductor film 715 may be formed as follows:gallium oxide whose composition is Ga₂O_(X) (X=3+α, 0<α<1) is formed andgallium aluminum oxide (aluminum gallium oxide) whose composition isGa_(X)Al_(2−X)O_(3+α) (0<X<2, 0<α<1) may be formed thereover. Note thatthe insulating film on the lower side of the oxide semiconductor film715 may be formed by a stack of insulating films each including a regionwhere the proportion of oxygen is higher than that in the stoichiometriccomposition. Alternatively, both the insulating films on the upper sideand the lower side of the oxide semiconductor film 715 may be formed bya stack of insulating films each including a region where the proportionof oxygen is higher than that in the stoichiometric composition.

Next, as illustrated in FIG. 8C, an insulating film 722 is formed so asto cover the gate insulating film 719, the conductive film 721, and thegate electrode 720. The insulating film 722 can be formed by PVD, CVD,or the like. The insulating film 722 can be formed using a materialincluding an inorganic insulating material such as silicon oxide,silicon oxynitride, silicon nitride, hafnium oxide, gallium oxide, oraluminum oxide. Note that for the insulating film 722, a material with alow dielectric constant or a structure with a low dielectric constant(e.g., a porous structure) is preferably used. When the dielectricconstant of the insulating film 722 is lowered, parasitic capacitancegenerated between wirings or electrodes can be reduced, which results inhigher speed operation. Note that although the insulating film 722 has asingle-layer structure in this embodiment, an embodiment of the presentinvention is not limited to this structure. The insulating film 722 mayhave a layered structure of two or more layers.

Next, an opening 725 is formed in the gate insulating film 719 and theinsulating film 722, so that part of the conductive film 718 is exposed.After that, a wiring 726 which is in contact with the conductive film718 through the opening 725 is formed over the insulating film 722.

A conductive film is formed by PVD or CVD and then is patterned, so thatthe wiring 726 is formed. As the material of the conductive film, anelement selected from aluminum, chromium, copper, tantalum, titanium,molybdenum, or tungsten; an alloy containing any of these elements as acomponent; or the like can be used. A material including one ofmanganese, magnesium, zirconium, beryllium, neodymium, and scandium or acombination of any of these elements may be used.

In this embodiment, as the wiring 726, a conductive film formed asfollows is used: by a sputtering method, a titanium film with athickness of about 50 nm, an aluminum film with a thickness of about 200nm, and a titanium film with a thickness of about 50 nm are sequentiallystacked. Here, the titanium film formed has a function of reducing anoxide film (e.g., a native oxide film) formed on the surface over whichthe titanium film is formed, to decrease the contact resistance with thelower electrode or the like (here, the conductive film 718). With thetitanium film, hillock of aluminum film can be prevented. A copper filmmay be formed by a plating method after the formation of the barrierfilm of titanium, titanium nitride, or the like.

Next, an insulating film 727 is formed so as to cover the wiring 726.Through the series of steps, the memory device can be manufactured.

Note that in the manufacturing method, the conductive films 717 and 718functioning as source and drain electrodes are formed after theformation of the oxide semiconductor film 715. Thus, as illustrated inFIG. 8B, in the transistor 109 obtained by the manufacturing method, theconductive films 717 and 718 are formed over the oxide semiconductorfilm 715. However, in the transistor 109, the conductive filmsfunctioning as source and drain electrodes may be formed below the oxidesemiconductor film 715, that is, between the oxide semiconductor film715 and the insulating film 714.

This embodiment can be implemented by being combined as appropriate withany of the above embodiments.

Embodiment 5

In this embodiment, a transistor which includes an oxide semiconductorfilm and has a structure different from those in Embodiments 4 will bedescribed.

A transistor 601 illustrated in FIG. 9A is a bottom gate transistorhaving a channel-etched structure.

The transistor 601 includes a gate electrode 602 formed over aninsulating surface, a gate insulating film 603 over the gate electrode602, an oxide semiconductor film 604 which is over the gate insulatingfilm 603 and overlaps with the gate electrode 602, and a conductive film605 and a conductive film 606 formed over the oxide semiconductor film604. The transistor 601 may further include an insulating film 607formed over the oxide semiconductor film 604 and the conductive film 605and the conductive film 606.

Note that the transistor 601 illustrated in FIG. 9A may further includea back-gate electrode which is over the insulating film 607 and which ispresent in a portion overlapping with the oxide semiconductor film 604.

A transistor 611 illustrated in FIG. 9B is a channel-protectivebottom-gate transistor.

The transistor 611 includes a gate electrode 612 formed over aninsulating surface, a gate insulating film 613 over the gate electrode612, an oxide semiconductor film 614 which is over the gate insulatingfilm 613 and overlaps with the gate electrode 612, a channel protectivefilm 618 formed over the oxide semiconductor film 614, and a conductivefilm 615 and a conductive film 616 formed over the oxide semiconductorfilm 614. The transistor 611 may further include an insulating film 617formed over the channel protective film 618, the conductive film 615,and the conductive film 616.

The transistor 611 illustrated in FIG. 9B may further include aback-gate electrode formed over the insulating film 617 in a portionwhich overlaps with the oxide semiconductor film 614.

The channel protective film 618 can prevent the portion of the oxidesemiconductor film 614, which serves as a channel formation region, frombeing damaged in a subsequent step (for example, a reduction inthickness due to plasma or an etchant in etching). Consequently,reliability of the transistor 611 can be improved.

A transistor 621 illustrated in FIG. 9C is a bottom-contact bottom-gatetransistor.

The transistor 621 includes a gate electrode 622 over an insulatingsurface; a gate insulating film 623 over the gate electrode 622; aconductive film 625 and a conductive film 626 over the gate insulatingfilm 623; and an oxide semiconductor film 624 which overlaps with thegate insulating film 623 and overlaps with the gate electrode 622 andwhich is formed over the conductive film 625 and the conductive film626. The transistor 621 may further include an insulating film 627formed over the conductive film 625, the conductive film 626, and theoxide semiconductor film 624.

The transistor 621 illustrated in FIG. 9C may further include aback-gate electrode formed over the insulating film 627 in a portionwhich overlaps with the oxide semiconductor film 624.

The transistor 641 includes conductive films 645 and 646 formed over aninsulating surface; an oxide semiconductor film 644 formed overconductive films 645 and 646; a gate insulating film 643 formed over theoxide semiconductor film 644, the conductive film 645, and theconductive film 646; a gate electrode 642 which overlaps with the oxidesemiconductor film 644, over the gate insulating film 643. Further, thetransistor 641 may include an insulating film 647 formed over the gateelectrode 642.

This embodiment can be implemented by being combined as appropriate withany of the above embodiments.

Embodiment 6

In this embodiment, a transistor which includes an oxide semiconductorfilm and has a structure different from those in Embodiments 4 and 5will be described.

A transistor 901 illustrated in FIG. 10A includes an oxide semiconductorfilm 903 which is formed over an insulating film 902 and functions as anactive layer; a source electrode 904 and a drain electrode 905 which areformed over the oxide semiconductor film 903; a gate insulating film 906which is formed over the oxide semiconductor film 903, the sourceelectrode 904, and the drain electrode 905; and a gate electrode 907overlaps with the oxide semiconductor film 903, over the gate insulatingfilm 906.

The transistor 901 illustrated in FIG. 10A is a top-gate transistor inwhich the gate electrode 907 is formed over the oxide semiconductor film903, and a top-contact transistor in which the source electrode 904 andthe drain electrode 905 are formed over the oxide semiconductor film903. In the transistor 901, the source electrode 904 and the drainelectrode 905 do not overlap with the gate electrode 907. That is tosay, a distance larger than the thickness of the gate insulating film906 is provided between the gate electrode 907, and the source electrode904 or the drain electrode 905. Therefore, in the transistor 901,parasitic capacitance generated between the gate electrode 907, and thesource electrode 904 or the drain electrode 905 can be small, so thathigh-speed operation can be achieved.

The oxide semiconductor film 903 includes a pair of high concentrationregions 908, which is obtained by adding a dopant imparting n-typeconductivity to the oxide semiconductor film 903 after formation of thegate electrode 907. Further, in the oxide semiconductor film 903, aregion which overlaps with the gate electrode 907 with the gateinsulating film 906 provided therebetween is a channel formation region909. In the oxide semiconductor film 903, the channel formation region909 is provided between the pair of high concentration regions 908. Ionimplantation can be used for addition of the dopant, which is performedto form the high concentration region 908. A rare gas such as helium,argon, and xenon; an atom belonging to Group 15, such as nitrogen,phosphorus, arsenic, and antimony; or the like can be used as thedopant.

For example, when nitrogen is used as the dopant, it is preferable thatthe high concentration regions 908 have a nitrogen atom concentrationhigher than or equal to 5×10¹⁹/cm³ and lower than or equal to1×10²²/cm³.

The high concentration regions 908 to which the dopant imparting n-typeconductivity is added has higher conductivity than other regions in theoxide semiconductor film 903. Thus, the high concentration regions 908are provided in the oxide semiconductor film 903, whereby a resistancebetween the source electrode 904 and the drain electrode 905 can bereduced.

When an In—Ga—Zn-based oxide semiconductor is used for the oxidesemiconductor film 903, heat treatment is performed for approximately 1hour at a temperature higher than or equal to 300° C. and lower than orequal to 600° C. after the addition of nitrogen, so that an oxidesemiconductor in the high concentration regions 908 has a wurtzitecrystal structure. When the oxide semiconductor in the highconcentration regions 908 has a wurtzite crystal structure, theconductivity of the high concentration regions 908 can be furtherincreased and the resistance between the source electrode 904 and thedrain electrode 905 can be further reduced. Note that in order toeffectively reduce the resistance between the source electrode 904 andthe drain electrode 905 by forming the oxide semiconductor having awurtzite crystal structure, when nitrogen is used as the dopant, thenitrogen atom concentration in the high concentration regions 908 ispreferably higher than or equal to 1×10²⁰/cm³ and lower than or equal to7 atoms %. However, even when the nitrogen atom concentration is lowerthan the above range, the oxide semiconductor having a wurtzite crystalstructure can be obtained in some cases.

Further, the oxide semiconductor film 903 may be a CAAC-OS film. In thatcase, the conductivity of the oxide semiconductor film 903 can be highas compared to that in the case of an amorphous semiconductor film;therefore, the resistance between the source electrode 904 and the drainelectrode 905 can be reduced.

The reduction in the resistance between the source electrode 904 and thedrain electrode 905 ensures a high on-state current and high-speedoperation even when the transistor 901 is miniaturized. Further, theminiaturization of the transistor 901 makes it possible to reduce anarea occupied by a memory cell and increase memory capacitance per unitarea of a cell array.

A transistor 911 illustrated in FIG. 10B includes a source electrode 914and a drain electrode 915 which are formed over an insulating film 912;an oxide semiconductor film 913 which is formed over the sourceelectrode 914 and the drain electrode 915 and functions as an activelayer; a gate insulating film 916 over the oxide semiconductor film 913,the source electrode 914, and the drain electrode 915; and a gateelectrode 917 over the gate insulating film 916, provided in a positionoverlapping with the oxide semiconductor film 913.

The transistor 911 illustrated in FIG. 10B is a top-gate transistor inwhich the gate electrode 917 is formed over the oxide semiconductor film913, and is a bottom-contact transistor in which the source electrode914 and the drain electrode 915 are formed below the oxide semiconductorfilm 913. In a similar manner to the transistor 901, the sourceelectrode 914 and the drain electrode 915 do not overlap with the gateelectrode 917 in the transistor 911. Thus, parasitic capacitances formedbetween the source electrode 914 and the gate electrode 917 and betweenthe drain electrode 915 and the gate electrode 917 can be reduced andhigh-speed operation can be achieved.

In addition, the oxide semiconductor film 913 includes a pair of highconcentration regions 918 which is obtained by addition of a dopantimparting n-type conductivity to the oxide semiconductor film 913 afterthe gate electrode 917 is formed. Further, in the oxide semiconductorfilm 913, a region which overlaps with the gate electrode 917 with thegate insulating film 916 provided therebetween is a channel formationregion 919. A channel formation region 919 is provided between the pairof high concentration regions 918 in the oxide semiconductor film 913.

The high concentration regions 918 can be formed by an ion implantationmethod in a similar manner to the case of the high concentration regions908 included in the transistor 901. The case of the high concentrationregions 908 can be referred to for kinds of dopant for forming the highconcentration regions 918.

For example, when nitrogen is used as the dopant, it is preferable thatthe high concentration regions 918 have a nitrogen atom concentrationhigher than or equal to 5×10¹⁹/cm³ and lower than or equal to1×10²²/cm³.

The high concentration regions 918 to which the dopant imparting n-typeconductivity is added has higher conductivity than other regions in theoxide semiconductor film 913. Thus, the high concentration regions 918are included in the oxide semiconductor film 913, which results in areduction in resistance between the source electrode 914 and the drainelectrode 915.

When an In—Ga—Zn-based oxide semiconductor is used for the oxidesemiconductor film 913, heat treatment is performed at a temperaturehigher than or equal to 300° C. and lower than or equal to 600° C. afterthe addition of nitrogen, so that an oxide semiconductor in the highconcentration regions 918 has a wurtzite crystal structure. When theoxide semiconductor in the high concentration regions 918 has a wurtzitecrystal structure, the conductivity of the high concentration regions918 can be further increased and the resistance between the sourceelectrode 914 and the drain electrode 915 can be further reduced. Notethat in order to effectively reduce the resistance between the sourceelectrode 914 and the drain electrode 915 by forming the oxidesemiconductor having a wurtzite crystal structure, when nitrogen is usedas a dopant, the nitrogen atom concentration in the high concentrationregions 918 is preferably higher than or equal to 1×10²⁰/cm³ and lowerthan or equal to 7 atoms %. However, even when the nitrogen atomconcentration is lower than the above range, the oxide semiconductorhaving a wurtzite crystal structure can be obtained in some cases.

Further, the oxide semiconductor film 913 may be a CAAC-OS film. In thatcase, the conductivity of the oxide semiconductor film 913 can be highas compared to that in the case of an amorphous semiconductor film, andthus the resistance between the source electrode 914 and the drainelectrode 915 can be reduced.

The reduction in the resistance between the source electrode 914 and thedrain electrode 915 ensures a high on-state current and high-speedoperation even when the transistor 911 is miniaturized. Further, theminiaturization of the transistor 911 makes it possible to reduce anarea occupied by a memory cell and increase memory capacity per unitarea of a cell array.

A transistor 921 illustrated in FIG. 10C includes an oxide semiconductorfilm 923 which is formed over an insulating film 922 and functions as anactive layer; a source electrode 924 and a drain electrode 925 which areformed over the oxide semiconductor film 923; a gate insulating film 926over the oxide semiconductor film 923, the source electrode 924, and thedrain electrode 925; and a gate electrode 927 over the gate insulatingfilm 926, provided in a position overlapping with the oxidesemiconductor film 923. The transistor 921 further includes sidewalls930 provided on the side of the gate electrode 927 and formed using aninsulating film.

The transistor 921 illustrated in FIG. 10C is a top-gate transistor inwhich the gate electrode 927 is formed over the oxide semiconductor film923, and also is a top-contact transistor in which the source electrode924 and the drain electrode 925 are formed over the oxide semiconductorfilm 923. Since the source electrode 924 and the drain electrode 925 donot overlap with the gate electrode 927 in the transistor 921 in asimilar manner to the transistor 901, parasitic capacitances between thesource electrode 924 and the gate electrode 927 and between the drainelectrode 925 and the gate electrode 927 can be reduced and high-speedoperation can be achieved.

Further, the oxide semiconductor film 923 includes a pair of highconcentration regions 928 and a pair of low concentration regions 929which can be obtained by the addition of a dopant imparting n-typeconductivity to the oxide semiconductor film 923 after the gateelectrode 927 is formed. Furthermore, in the oxide semiconductor film923, a region which overlaps with the gate electrode 927 with the gateinsulating film 926 provided therebetween is a channel formation region931. In the oxide semiconductor film 923, the pair of low concentrationregions 929 is provided between the pair of high concentration regions928, and the channel formation region 931 is provided between the pairof low concentration regions 929. The pair of low concentration regions929 is provided in regions which are included in the oxide semiconductorfilm 923 and overlap with the sidewalls 930 with the gate insulatingfilm 926 provided therebetween.

The high concentration regions 928 and the low concentration regions 929can be formed by an ion implantation method in a similar manner to thecase of the high concentration regions 908 included in the transistor901. The case of the high concentration regions 908 can be referred tofor kinds of dopant for forming the high concentration regions 928.

For example, when nitrogen is used as the dopant, it is preferable thatthe high concentration regions 928 have a nitrogen atom concentrationhigher than or equal to 5×10¹⁹/cm³ and lower than or equal to1×10²²/cm³. Further, when nitrogen is used as the dopant, for example,it is preferable that the low concentration regions 929 have a nitrogenatom concentration higher than or equal to 5×10¹⁸/cm³ and lower than5×10¹⁹/cm³.

The high concentration regions 928 to which the dopant imparting n-typeconductivity is added have higher conductivity than other regions in theoxide semiconductor film 923. Thus, the high concentration regions 928are provided in the oxide semiconductor film 923, which results in areduction in resistance between the source electrode 924 and the drainelectrode 925. Further, the low concentration regions 929 are providedbetween the channel formation region 931 and the high concentrationregions 928, which results in a reduction in negative shift of athreshold voltage due to a short-channel effect.

When an In—Ga—Zn-based oxide semiconductor is used for the oxidesemiconductor film 923, heat treatment is performed at a temperaturehigher than or equal to 300° C. and lower than or equal to 600° C. afterthe addition of nitrogen, so that an oxide semiconductor in the highconcentration regions 928 has a wurtzite crystal structure. Further, thelow concentration regions 929 may have a wurtzite crystal structure bythe heat treatment depending on the concentration of the nitrogen. Whenthe oxide semiconductor in the high concentration regions 928 has awurtzite crystal structure, the conductivity of the high concentrationregions 928 can be further increased and the resistance between thesource electrode 924 and the drain electrode 925 can be further reduced.Note that in order to effectively reduce the resistance between thesource electrode 924 and the drain electrode 925 by forming the oxidesemiconductor having a wurtzite crystal structure, when nitrogen is usedas a dopant, the nitrogen atom concentration in the high concentrationregions 928 is preferably higher than or equal to 1×10²⁰/cm³ and lowerthan or equal to 7 atoms %. However, even when the nitrogen atomconcentration is lower than the above range, the oxide semiconductorhaving a wurtzite crystal structure can be obtained in some cases.

Further, the oxide semiconductor film 923 may be a CAAC-OS film. In thatcase, the conductivity of the oxide semiconductor film 923 can be highas compared to that in the case of an amorphous semiconductor film, andthus the resistance between the source electrode 924 and the drainelectrode 925 can be reduced.

The reduction in the resistance between the source electrode 924 and thedrain electrode 925 ensures a high on-state current and high-speedoperation even when the transistor 921 is miniaturized. Further, theminiaturization of the transistor 921 makes it possible to reduce anarea occupied by a memory cell and increase memory capacity per unitarea of a cell array.

A transistor 941 illustrated in FIG. 10D includes a source electrode 944and a drain electrode 945 which are formed over an insulating film 942;an oxide semiconductor film 943 which is formed over the sourceelectrode 944 and the drain electrode 945 and functions as an activelayer; a gate insulating film 946 over the oxide semiconductor film 943,the source electrode 944, and the drain electrode 945; and a gateelectrode 947 over the gate insulating film 946, provided in a positionoverlapping with the oxide semiconductor film 943. The transistor 941further includes sidewalls 950 which is provided on the side of the gateelectrode 947 and formed using an insulating film.

The transistor 941 illustrated in FIG. 10D is a top-gate transistor inwhich the gate electrode 947 is formed over the oxide semiconductor film943, and is a bottom-contact transistor in which the source electrode944 and the drain electrode 945 are formed below the oxide semiconductorfilm 943. Since the source electrode 944 and the drain electrode 945 donot overlap with the gate electrode 947 in the transistor 941 in asimilar manner to the transistor 901, parasitic capacitances between thesource electrode 944 and the gate electrode 947 and between the drainelectrode 945 and the gate electrode 947 can be reduced and high-speedoperation can be achieved.

Further, the oxide semiconductor film 943 includes a pair of highconcentration regions 948 and a pair of low concentration regions 949which can be obtained by the addition of a dopant imparting n-typeconductivity to the oxide semiconductor film 943 after the gateelectrode 947 is formed. Furthermore, in the oxide semiconductor film943, a region which overlaps with the gate electrode 947 with the gateinsulating film 946 provided therebetween is a channel formation region951. In the oxide semiconductor film 943, the pair of low concentrationregions 949 is provided between the pair of high concentration regions948, and the channel formation region 951 is provided between the pairof low concentration regions 949. The pair of low concentration regions949 is provided in a region which is included in the oxide semiconductorfilm 943 and overlaps with the sidewalls 950 with the gate insulatingfilm 946 provided therebetween.

The high concentration regions 948 and the low concentration regions 949can be formed by an ion implantation method in a similar manner to thecase of the high concentration regions 908 included in the transistor901. The case of the high concentration regions 908 can be referred tofor kinds of dopant for forming the high concentration regions 948.

For example, when nitrogen is used as the dopant, it is preferable thatthe high concentration regions 948 have a nitrogen atom concentrationhigher than or equal to 5×10¹⁹/cm³ and lower than or equal to1×10²²/cm³. Further, when nitrogen is used as the dopant, for example,it is preferable that the low concentration regions 949 have a nitrogenatom concentration higher than or equal to 5×10¹⁸/cm³ and lower than5×10¹⁹/cm³.

The high concentration regions 948 to which the dopant imparting n-typeconductivity is added has higher conductivity than other regions in theoxide semiconductor film 943. Thus, the high concentration regions 948are included in the oxide semiconductor film 943, which results in areduction in resistance between the source electrode 944 and the drainelectrode 945. Further, the low concentration regions 949 are providedbetween the channel formation region 951 and the high concentrationregions 948, which results in a reduction in negative shift of athreshold voltage due to a short-channel effect.

When an In—Ga—Zn-based oxide semiconductor is used for the oxidesemiconductor film 943, heat treatment at a temperature higher than orequal to 300° C. and lower than or equal to 600° C. after the additionof nitrogen enables an oxide semiconductor in the high concentrationregions 948 to include a wurtzite crystal structure. Further, the lowconcentration regions 949 may include a wurtzite crystal structure bythe heat treatment depending on the concentration of the nitrogen. Whenthe oxide semiconductor in the high concentration regions 948 includes awurtzite crystal structure, the conductivity of the high concentrationregions 948 can be further increased and the resistance between thesource electrode 944 and the drain electrode 945 can be further reduced.Note that in order to effectively reduce the resistance between thesource electrode 944 and the drain electrode 945 by forming the oxidesemiconductor having a wurtzite crystal structure, when nitrogen is usedas a dopant, the nitrogen atom concentration in the high concentrationregions 948 is preferably higher than or equal to 1×10²⁰/cm³ and lowerthan or equal to 7 atoms %. However, even when the nitrogen atomconcentration is lower than the above range, the oxide semiconductorhaving a wurtzite crystal structure can be obtained in some cases.

Further, the oxide semiconductor film 943 may be a CAAC-OS film. In thatcase, the conductivity of the oxide semiconductor film 943 can be highas compared to that in the case of an amorphous semiconductor film, andthus the resistance between the source electrode 944 and the drainelectrode 945 can be reduced.

The reduction in the resistance between the source electrode 944 and thedrain electrode 945 ensures a high on-state current and high-speedoperation even when the transistor 941 is miniaturized. Further, theminiaturization of the transistor 941 makes it possible to reduce anarea occupied by a memory cell and increase memory capacity per unitarea of a cell array.

Note that, as one of methods for manufacturing high concentrationregions functioning as a source region and a drain region in atransistor including an oxide semiconductor by a self-aligned process, amethod is disclosed in which a surface of an oxide semiconductor film isexposed and argon plasma treatment is performed to reduce resistance ofthe region in the oxide semiconductor film which is exposed to plasma(S. Jeon et al. “180 nm Gate Length Amorphous InGaZnO Thin FilmTransistor for High Density Image Sensor Application”, IEDM Tech. Dig.,p. 504, 2010).

However, in the manufacturing method, a gate insulating film needs to bepartly removed after formation of the gate insulating film so thatportions which are to serve as the source region and the drain regionare exposed. At the time of partly removing the gate insulating film,part of an oxide semiconductor film below the gate insulating film isover-etched, so that the thicknesses of the portions which are to serveas the source region and the drain region are reduced. As a result, theresistance of the source region and the drain region is increased, andcharacteristic defect due to the over etching is likely to occur.

To miniaturize a transistor, it is necessary to employ a dry etchingmethod with high processing accuracy. However, the above over etching ismore likely to occur when a dry etching method which does notsufficiently ensure selectivity between the oxide semiconductor film andthe gate insulating film.

For example, no problem is caused when the oxide semiconductor film hasa sufficient thickness, but in the case where a channel length is 200 nmor less, it is necessary that a portion of the oxide semiconductor film,which is to serve as a channel formation region, be 20 nm or less,preferably 10 nm or less, in order to prevent a short-channel effect.When such a thin oxide semiconductor film is used, the over etching ofthe oxide semiconductor film is not preferable because the over etchingcauses a characteristic defect of the transistor, as described above.

However, when a dopant is added to the oxide semiconductor in the statewhere the oxide semiconductor film is not exposed and a gate insulatingfilm remains, as described in an embodiment of the present invention,the over etching of the oxide semiconductor film can be prevented andexcessive damage to the oxide semiconductor film can be reduced. Inaddition, an interface between the oxide semiconductor film and the gateinsulating film is kept clean. Consequently, characteristics andreliability of the transistor can be improved.

This embodiment can be implemented by being combined as appropriate withany of the above embodiments.

Embodiment 7

In the memory device which is an embodiment of the present invention, adriver circuit may include a transistor which is manufactured using abulk single crystal semiconductor substrate. In FIG. 12, across-sectional view of a memory device in which a transistor includingan oxide semiconductor and a capacitor are formed over a transistorwhich is formed using the bulk single crystal semiconductor substrate isillustrated as an example

The memory device illustrated in FIG. 12 includes an n-channeltransistor 661 and a p-channel transistor 662 which are provided over asemiconductor substrate 660, a transistor 664 which is provided over aninsulating film 663 covering the n-channel transistor 661 and thep-channel transistor 662 and which includes an oxide semiconductor, anda capacitor 665.

Although the case where the transistor 664 includes an oxidesemiconductor in a channel formation region and has a structuredescribed in Embodiment 4 is described as an example, the structure maybe that described in Embodiment 5 or 6.

The semiconductor substrate 660 can be, for example, a single crystalsilicon substrate having n-type or p-type conductivity, a compoundsemiconductor substrate (e.g., a GaAs substrate, an InP substrate, a GaNsubstrate, a SiC substrate, a sapphire substrate, or a ZnSe substrate),or the like. In FIG. 12, the case where a single crystal siliconsubstrate having n-type conductivity is used is illustrated as anexample.

In addition, the n-channel transistor 661 and the p-channel transistor662 are electrically isolated by an element isolation insulating film666. For formation of the element isolation insulating film 666, aselective oxidation method (local oxidation of silicon (LOCOS) method),a trench isolation method, or the like can be used.

In a region where the p-channel transistor 662 is formed, a regioncalled a p-well 667 is formed by selectively introducing an impurityelement imparting p-type conductivity. In the case where a semiconductorsubstrate having p-type conductivity is used, an impurity elementimparting n-type conductivity may be selectively introduced to a regionwhere the n-channel transistor 661 is formed, so that an n-well may beformed.

This embodiment can be implemented by being combined as appropriate withany of the above embodiments.

Embodiment 8

An oxide semiconductor preferably contains at least indium (In) or zinc(Zn). In particular, both In and Zn are preferably contained.

As a stabilizer for reducing variation in electric characteristics of atransistor including the oxide semiconductor, it is preferable that oneor more selected from gallium (Ga), tin (Sn), hafnium (Hf), aluminum(Al), or lanthanoid be contained.

As lanthanoid, lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium(Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb),dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium(Yb), or lutetium (Lu) can be given.

As a single-component metal oxide included in the oxide semiconductor,including indium (In) or zinc (Zn), for example, an indium oxide, a zincoxide, or the like can be used.

As a two-component metal oxide included in the oxide semiconductor,including indium (In) or zinc (Zn), for example, an In—Zn-based oxide, aSn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, aSn—Mg-based oxide, an In—Mg-based oxide, an In—Ga-based oxide, or thelike can be used.

As a three-component metal oxide included in the oxide semiconductor,including indium (In) or zinc (Zn), for example, an In—Ga—Zn-based oxide(also referred to as IGZO), an In—Sn—Zn-based oxide, a Sn—Ga—Zn-basedoxide, an In—Al—Zn-based oxide, an In—Hf—Zn-based oxide, anIn—La—Zn-based oxide, an In—Ce—Zn-based oxide, an In—Pr—Zn-based oxide,an In—Nd—Zn-based oxide, an In—Sm—Zn-based oxide, an In—Eu—Zn-basedoxide, an In—Gd—Zn-based oxide, an In—Tb—Zn-based oxide, anIn—Dy—Zn-based oxide, an In—Ho—Zn-based oxide, an In—Er—Zn-based oxide,an In—Tm—Zn-based oxide, an In—Yb—Zn-based oxide, an In—Lu—Zn-basedoxide, an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide, or the like canbe used.

As a four-component metal oxide included in the oxide semiconductor,including indium (In) or zinc (Zn), for example, an In—Sn—Ga—Zn-basedoxide, an In—Hf—Ga—Zn-based oxide, an In—Al—Ga—Zn-based oxide, anIn—Sn—Al—Zn-based oxide, an In—Sn—Hf—Zn-based oxide, anIn—Hf—Al—Zn-based oxide, or the like can be used.

Note that, for example, an “In—Ga—Zn-based oxide” means an oxidecontaining In, Ga, and Zn as its main components and there is noparticular limitation on the ratio of In, Ga, and Zn. The In—Ga—Zn-basedoxide may contain another metal element in addition to In, Ga, and Zn.

For example, an In—Ga—Zn-based oxide with an atomic ratio ofIn:Ga:Zn=1:1:1 (=1/3:1/3:1/3) or In:Ga:Zn=2:2:1 (=2/5:2/5:1/5), or anoxide with an atomic ratio close to the above atomic ratios can be used.

Alternatively, an In—Sn—Zn-based oxide with an atomic ratio ofIn:Sn:Zn=1:1:1 (=1/3: 1/3: 1/3), In:Sn:Zn=2:1:3 (=1/3: 1/6: 1/2), orIn:Sn:Zn=2:1:5 (=1/4: 1/8: 5/8), or any of oxides whose composition isin the neighborhood of the above compositions may be used.

However, without limitation to the materials given above, a materialwith an appropriate composition may be used depending on neededsemiconductor characteristics (e.g., mobility, threshold voltage, andvariation). In order to obtain the needed semiconductor characteristics,it is preferable that the carrier density, the impurity concentration,the defect density, the atomic ratio between a metal element and oxygen,the interatomic distance, the density, and the like be set toappropriate values.

In the case where the oxide semiconductor is non-single-crystal, theoxide semiconductor may be either amorphous or polycrystalline. Further,the oxide semiconductor may have a structure including a crystallineportion in an amorphous portion. Note that it is preferable to usenon-amorphous because amorphous includes many defects.

This embodiment can be implemented by being combined as appropriate withany of the above embodiments.

Embodiment 9

In this embodiment, an oxide including a crystal with c-axis alignment(also referred to as C-Axis Aligned Crystal (CAAC)), which has atriangular or hexagonal atomic arrangement when seen from the directionof an a-b plane, a surface, or an interface, and in which metal atomsare arranged in a layered manner, or metal atoms and oxygen atoms arearranged in a layered manner along the c-axis, and the direction of thea-axis or the b-axis is varied in the a-b plane (the crystal rotatesaround the c-axis) will be described.

In a broad sense, an oxide including CAAC means a non-single-crystaloxide including a phase which has a triangular, hexagonal, regulartriangular, or regular hexagonal atomic arrangement when seen from thedirection perpendicular to the a-b plane and in which metal atoms arearranged in a layered manner or metal atoms and oxygen atoms arearranged in a layered manner when seen from the direction perpendicularto the c-axis direction.

The CAAC is not a single crystal, but this does not mean that the CAACis composed of only an amorphous component. Although the CAAC includes acrystallized portion (crystalline portion), a boundary between onecrystalline portion and another crystalline portion is not clearlydetermined in some cases.

Nitrogen may be substituted for part of oxygen included in the CAAC. Thec-axes of individual crystalline portions included in the CAAC may bealigned in a certain direction (e.g., a direction perpendicular to asurface of a substrate over which the CAAC is formed or a surface of theCAAC). Alternatively, the normals of the a-b planes of the individualcrystalline portions included in the CAAC may be aligned in a certaindirection (e.g., a direction perpendicular to a surface of a substrateover which the CAAC is formed or a surface of the CAAC).

The CAAC becomes a conductor, a semiconductor, or an insulator dependingon its composition or the like. The CAAC transmits or does not transmitvisible light depending on its composition or the like.

As an example of such a CAAC, there is a crystal which is formed into afilm shape and has a triangular or hexagonal atomic arrangement whenobserved from the direction perpendicular to a surface of the film or asurface of a supporting substrate, and in which metal atoms are arrangedin a layered manner or metal atoms and oxygen atoms (or nitrogen atoms)are arranged in a layered manner when a cross section of the film isobserved.

An example of a crystal structure of the CAAC will be described indetail with reference to FIGS. 13A to 13E, FIGS. 14A to 14C, and FIGS.15A to 15C. In FIGS. 13A to 13E, FIGS. 14A to 14C, and FIGS. 15A to 15C,the vertical direction corresponds to the c-axis direction and a planeperpendicular to the c-axis direction corresponds to the a-b plane,unless otherwise specified. When the expressions “an upper half” and “alower half” are simply used, they refer to an upper half above the a-bplane and a lower half below the a-b plane (an upper half and a lowerhalf with respect to the a-b plane). Furthermore, in FIGS. 13A to 13E, Osurrounded by a circle represents tetracoordinate O and O surrounded bya double circle represents tricoordinate O.

FIG. 13A illustrates a structure including one hexacoordinate In atomand six tetracoordinate oxygen (hereinafter referred to astetracoordinate O) atoms proximate to the In atom. Here, a structureincluding one metal atom and oxygen atoms proximate thereto is referredto as a small group. The structure in FIG. 13A is actually an octahedralstructure, but is illustrated as a planar structure for simplicity. Notethat three tetracoordinate O atoms exist in each of an upper half and alower half in FIG. 13A. In the small group illustrated in FIG. 13A,electric charge is 0.

FIG. 13B illustrates a structure including one pentacoordinate Ga atom,three tricoordinate oxygen (hereinafter referred to as tricoordinate O)atoms proximate to the Ga atom, and two tetracoordinate O atomsproximate to the Ga atom. All of the tricoordinate O atoms exist on thea-b plane. One tetracoordinate O atom exists in each of an upper halfand a lower half in FIG. 13B. An In atom can also have the structureillustrated in FIG. 13B because an In atom can have five ligands. In thesmall group illustrated in FIG. 13B, electric charge is 0.

FIG. 13C illustrates a structure including one tetracoordinate Zn atomand four tetracoordinate O atoms proximate to the Zn atom. In FIG. 13C,one tetracoordinate O atom exists in an upper half and threetetracoordinate O atoms exist in a lower half. Alternatively, threetetracoordinate O atoms may exist in the upper half and onetetracoordinate O atom may exist in the lower half in FIG. 13C. In thesmall group illustrated in FIG. 13C, electric charge is 0.

FIG. 13D illustrates a structure including one hexacoordinate Sn atomand six tetracoordinate O atoms proximate to the Sn atom. In FIG. 13D,three tetracoordinate O atoms exist in each of an upper half and a lowerhalf. In the small group illustrated in FIG. 13D, electric charge is +1.

FIG. 13E illustrates a small group including two Zn atoms. In FIG. 13E,one tetracoordinate O atom exists in each of an upper half and a lowerhalf. In the small group illustrated in FIG. 13E, electric charge is −1.

Here, a plurality of small groups form a medium group, and a pluralityof medium groups form a large group (also referred to as a unit cell).

Now, a rule of bonding between the small groups will be described. Thethree O atoms in the upper half with respect to the hexacoordinate Inatom in FIG. 13A each have three proximate In atoms in the downwarddirection, and the three O atoms in the lower half each have threeproximate In atoms in the upward direction. The one O atom in the upperhalf with respect to the pentacoordinate Ga atom in FIG. 13B has oneproximate Ga atom in the downward direction, and the one O atom in thelower half has one proximate Ga atom in the upward direction. The one Oatom in the upper half with respect to the tetracoordinate Zn atom inFIG. 13C has one proximate Zn atom in the downward direction, and thethree O atoms in the lower half each have three proximate Zn atoms inthe upward direction. In this manner, the number of the tetracoordinateO atoms above the metal atom is equal to the number of the metal atomsproximate to and below each of the tetracoordinate O atoms. Similarly,the number of the tetracoordinate O atoms below the metal atom is equalto the number of the metal atoms proximate to and above each of thetetracoordinate O atoms. Since the coordination number of thetetracoordinate O atom is 4, the sum of the number of the metal atomsproximate to and below the O atom and the number of the metal atomsproximate to and above the O atom is 4. Accordingly, when the sum of thenumber of tetracoordinate O atoms above a metal atom and the number oftetracoordinate O atoms below another metal atom is 4, the two kinds ofsmall groups including the metal atoms can be bonded. For example, inthe case where the hexacoordinate metal (In or Sn) atom is bondedthrough three tetracoordinate O atoms in the lower half, it is bonded tothe pentacoordinate metal (Ga or In) atom or the tetracoordinate metal(Zn) atom.

A metal atom whose coordination number is 4 is bonded to another metalatom through a tetracoordinate O atom in the c-axis direction. Inaddition to the above, a medium group can be formed in a differentmanner by combining a plurality of small groups so that the totalelectric charge of the layered structure is 0.

FIG. 14A illustrates a model of a medium group included in a layeredstructure of an In—Sn—Zn-based oxide. FIG. 14B illustrates a large groupincluding three medium groups. Note that FIG. 14C illustrates an atomicarrangement in the case where the layered structure in FIG. 14B isobserved from the c-axis direction.

In FIG. 14A, a tricoordinate O atom is omitted for simplicity, and atetracoordinate O atom is illustrated by a circle; the number in thecircle shows the number of tetracoordinate O atoms. For example, threetetracoordinate O atoms existing in each of an upper half and a lowerhalf with respect to a Sn atom are denoted by circled 3. Similarly, inFIG. 14A, one tetracoordinate O atom existing in each of an upper halfand a lower half with respect to an In atom is denoted by circled 1.FIG. 14A also illustrates a Zn atom proximate to one tetracoordinate Oatom in a lower half and three tetracoordinate O atoms in an upper half,and a Zn atom proximate to one tetracoordinate O atom in an upper halfand three tetracoordinate O atoms in a lower half.

In the medium group included in the layered structure of theIn—Sn—Zn-based oxide in FIG. 14A, in the order starting from the top, aSn atom proximate to three tetracoordinate O atoms in each of an upperhalf and a lower half is bonded to an In atom proximate to onetetracoordinate O atom in each of an upper half and a lower half, the Inatom is bonded to a Zn atom proximate to three tetracoordinate O atomsin an upper half, the Zn atom is bonded to an In atom proximate to threetetracoordinate O atoms in each of an upper half and a lower halfthrough one tetracoordinate O atom in a lower half with respect to theZn atom, the In atom is bonded to a small group that includes two Znatoms and is proximate to one tetracoordinate O atom in an upper half,and the small group is bonded to a Sn atom proximate to threetetracoordinate O atoms in each of an upper half and a lower halfthrough one tetracoordinate O atom in a lower half with respect to thesmall group. A plurality of such medium groups are bonded, so that alarge group is formed.

Here, electric charge for one bond of a tricoordinate O atom andelectric charge for one bond of a tetracoordinate O atom can be assumedto be −0.667 and −0.5, respectively. For example, electric charge of a(hexacoordinate or pentacoordinate) In atom, electric charge of a(tetracoordinate) Zn atom, and electric charge of a (pentacoordinate orhexacoordinate) Sn atom are +3, +2, and +4, respectively. Accordingly,electric charge in a small group including a Sn atom is +1. Therefore,electric charge of −1, which cancels +1, is needed to form a layeredstructure including a Sn atom. As a structure having electric charge of−1, the small group including two Zn atoms as illustrated in FIG. 13Ecan be given. For example, with one small group including two Zn atoms,electric charge of one small group including a Sn atom can be cancelled,so that the total electric charge of the layered structure can be 0.

When the large group illustrated in FIG. 14B is repeated, anIn—Sn—Zn-based oxide crystal (In₂SnZn₃O₈) can be obtained. Note that alayered structure of the obtained In—Sn—Zn-based oxide can be expressedas a composition formula, In₂SnZn₂O₇ (ZnO)_(m) (m is 0 or a naturalnumber).

The above-described rule also applies to the following oxides: afour-component metal oxide such as an In—Sn—Ga—Zn-based oxide; athree-component metal oxide such as an In—Ga—Zn-based oxide (alsoreferred to as IGZO), an In—Al—Zn-based oxide, a Sn—Ga—Zn-based oxide,an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide, an In—Hf—Zn-basedoxide, an In—La—Zn-based oxide, an In—Ce—Zn-based oxide, anIn—Pr—Zn-based oxide, an In—Nd—Zn-based oxide, an In—Sm—Zn-based oxide,an In—Eu—Zn-based oxide, an In—Gd—Zn-based oxide, an In—Tb—Zn-basedoxide, an In—Dy—Zn-based oxide, an In—Ho—Zn-based oxide, anIn—Er—Zn-based oxide, an In—Tm—Zn-based oxide, an In—Yb—Zn-based oxide,or an In—Lu—Zn-based oxide; a two-component metal oxide such as anIn—Zn-based oxide, a Sn—Zn-based oxide, an Al—Zn-based oxide, aZn—Mg-based oxide, a Sn—Mg-based oxide, an In—Mg-based oxide, or anIn—Ga-based oxide; and the like.

As an example, FIG. 15A illustrates a model of a medium group includedin a layered structure of an In—Ga—Zn-based oxide.

In the medium group included in the layered structure of theIn—Ga—Zn-based oxide in FIG. 15A, in the order starting from the top, anIn atom proximate to three tetracoordinate O atoms in each of an upperhalf and a lower half is bonded to a Zn atom proximate to onetetracoordinate O atom in an upper half, the Zn atom is bonded to a Gaatom proximate to one tetracoordinate O atom in each of an upper halfand a lower half through three tetracoordinate O atoms in a lower halfwith respect to the Zn atom, and the Ga atom is bonded to an In atomproximate to three tetracoordinate O atoms in each of an upper half anda lower half through one tetracoordinate O atom in a lower half withrespect to the Ga atom. A plurality of such medium groups are bonded, sothat a large group is formed.

FIG. 15B illustrates a large group including three medium groups. Notethat FIG. 15C illustrates an atomic arrangement in the case where thelayered structure in FIG. 15B is observed from the c-axis direction.

Here, since electric charge of a (hexacoordinate or pentacoordinate) Inatom, electric charge of a (tetracoordinate) Zn atom, and electriccharge of a (pentacoordinate) Ga atom are +3, +2, and +3, respectively,electric charge of a small group including any of an In atom, a Zn atom,and a Ga atom is 0. As a result, the total electric charge of a mediumgroup having a combination of such small groups is always 0.

In order to form the layered structure of the In—Ga—Zn-based oxide, alarge group can be formed using not only the medium group illustrated inFIG. 15A but also a medium group in which the arrangement of the Inatom, the Ga atom, and the Zn atom is different from that in FIG. 15A.

This embodiment can be implemented by being combined as appropriate withany of the above embodiments.

Embodiment 10

The actually measured mobility of an insulated gate transistor can belower than its original mobility because of a variety of reasons; thisphenomenon occurs not only in the case of using an oxide semiconductor.One of the reasons that reduce the mobility is a defect inside asemiconductor or a defect at an interface between the semiconductor andan insulating film. When a Levinson model is used, the mobility on theassumption that no defect exists inside the semiconductor can becalculated theoretically.

Assuming that the original mobility and the measured mobility of asemiconductor are μ₀ and μ, respectively, and a potential barrier (suchas a grain boundary) exists in the semiconductor, the mobility μ can beexpressed by the following Formula 1.

$\begin{matrix}{\mu = {\mu_{0}{\exp( {- \frac{E}{kT}} )}}} & \lbrack {{Formula}\mspace{14mu} 1} \rbrack\end{matrix}$

E represents the height of the potential barrier, k represents theBoltzmann constant, and T represents the absolute temperature. When thepotential barrier E is assumed to be attributed to a defect, the heightof the potential barrier can be expressed by the following Formula 2according to the Levinson model.

$\begin{matrix}{E = {\frac{e^{2}N^{2}}{n} = \frac{e^{3}N^{2}t}{\; C_{ox}V_{g}}}} & \lbrack {{Formula}\mspace{14mu} 2} \rbrack\end{matrix}$

Note that e represents the elementary charge, N represents the averagedefect density per unit area in a channel formation region, s representsthe permittivity of the semiconductor, n represents the number ofcarriers per unit area in the channel formation region, C_(ox)represents the capacitance per unit area, V_(g) represents the gatevoltage, and t represents the thickness of a channel formation region.In the case where the thickness of the semiconductor film is less thanor equal to 30 nm, the thickness of the channel formation region may beregarded as being the same as the thickness of the semiconductor film.

The drain current I_(d) in a linear region can be expressed by thefollowing Formula 3.

$\begin{matrix}{I_{d} = {\frac{W_{\mu}V_{g}V_{d}C_{ox}}{L}{\exp( {- \frac{E}{kT}} )}}} & \lbrack {{Formula}\mspace{14mu} 3} \rbrack\end{matrix}$

Note that L represents the channel length and W represents the channelwidth, and L and W are each 10 μm. In addition, V_(d) represents thedrain voltage.

When dividing both sides of the Formula 3 by V_(g) and then takinglogarithms of both sides, the following Formula 4 can be obtained.

$\begin{matrix}{{\ln( \frac{I_{d}}{V_{g}} )} = {{{\ln( \frac{W_{\mu}V_{d}C_{ox}}{L} )} - \frac{E}{kT}} = {{\ln( \frac{W_{\mu}V_{d}C_{ox}}{L} )} - \frac{e^{3}N^{2}t}{8{kT}\; ɛ\; C_{ox}V_{g}}}}} & \lbrack {{Formula}\mspace{14mu} 4} \rbrack\end{matrix}$

The right side of Formula 4 is a function of V_(g). From Formula 4, itis found that the defect density N can be obtained from the slope of aline with ln(I_(d)/V_(g)) as the ordinate and 1/V_(g) as the abscissa.That is, the defect density can be evaluated from the I_(d)−V_(g)characteristics of the transistor. The defect density N of an oxidesemiconductor in which the ratio of indium (In), tin (Sn), and zinc (Zn)is 1:1:1 is approximately 1×10¹²/cm².

On the basis of the defect density obtained in this manner, or the like,μ₀ can be calculated to be 120 cm²/Vs. The measured mobility μ of anIn—Sn—Zn-based oxide semiconductor including a defect is approximately35 cm²/Vs. However, assuming that no defect exists inside thesemiconductor and at the interface between the semiconductor and aninsulating film, the mobility μ₀ of the oxide semiconductor is expectedto be 120 cm²/Vs.

Note that even when no defect exists inside a semiconductor, scatteringat an interface between a channel formation region and a gate insulatingfilm affects the transport property of the transistor. In other words,the mobility μ₁ at a position that is distance x away from the interfacebetween the channel formation region and the gate insulating film can beexpressed by the following Formula 5.

$\begin{matrix}{\frac{1}{\mu_{1}} = {\frac{1}{\mu_{0}} + {\frac{D}{B}\exp \; ( \; {- \frac{x}{G}} )}}} & \lbrack {{Formula}\mspace{14mu} 5} \rbrack\end{matrix}$

D represents the electric field in the gate direction, and B and G areconstants. B and G can be obtained from actual measurement results;according to the above measurement results, B is 4.75×10⁷ cm/s and G is10 nm (the depth to which the influence of interface scatteringreaches). When D is increased (i.e., when the gate voltage isincreased), the second term of the right side of Formula 5 is increasedand accordingly the mobility μ₁ is decreased.

Calculation results of the mobility μ₂ of a transistor in which achannel formation region includes an ideal oxide semiconductor without adefect inside the semiconductor are shown in FIG. 16. For thecalculation, device simulation software Sentaurus Device manufactured bySynopsys, Inc. was used. In the calculation, the bandgap, the electronaffinity, the relative permittivity, and the thickness of the oxidesemiconductor were assumed to be 2.8 eV, 4.7 eV, 15, and 15 nm,respectively. These values were obtained by measurement of a thin filmthat was formed by a sputtering method.

Further, the work functions of a gate electrode, a source electrode, anda drain electrode were assumed to be 5.5 eV, 4.6 eV, and 4.6 eV,respectively. The thickness of a gate insulating film was assumed to be100 nm, and the relative permittivity thereof was assumed to be 4.1. Thechannel length L and the channel width W were each assumed to be 10 μm,and the drain voltage V_(d) was assumed to be 0.1 V.

As shown in the calculation result shown in FIG. 16, the mobility μ₂ hasa peak of more than 100 cm²/Vs at a gate voltage V_(g) that is a littleover 1 V and is decreased as the gate voltage V_(g) becomes higherbecause the influence of interface scattering is increased. Note that inorder to reduce interface scattering, it is preferable that a surface ofthe semiconductor film be flat at the atomic level (atomic layerflatness).

Calculation results of characteristics of minute transistors which aremanufactured using an oxide semiconductor having such a mobility areshown. The transistor used for the calculation has an oxidesemiconductor film in which a channel formation region is providedbetween a pair of n-type semiconductor region. In the calculation, theresistivities of the pair of n-type semiconductor region are 2×10⁻³ Ωcm.Note that the channel length L of this transistor is 33 nm and thechannel width W of this transistor is 40 nm. Further, the calculationwas performed under the condition that part of the semiconductor regionwhich overlaps with the sidewall is an offset region, assuming that asidewall is formed on the side walls of a gate electrode. For thecalculation, Sentaurus Device which is software manufactured bySynopsys, Inc. was used.

FIGS. 17A to 17C show the calculation result of the gate voltage (V_(g):a potential difference between the gate electrode and the sourceelectrode) dependence of the drain current (I_(d), a solid line) and themobility (μ, a dotted line) of the transistor. The drain current I_(d)is obtained by calculation under the assumption that the drain voltage(V_(d), a potential difference between the drain electrode and thesource electrode) is +1 V and the mobility μ is obtained by calculationunder the assumption that the drain voltage is +0.1 V.

FIG. 17A shows the gate voltage dependence of the transistor in the casewhere the thickness of the gate insulating film is 15 nm, FIG. 17B showsthat of the transistor in the case where the thickness of the gateinsulating film is 10 nm, and FIG. 17C shows that of the transistor inthe case where the thickness of the gate insulating film is 5 nm. As thegate insulating film is thinner, the drain current I_(d) (off-statecurrent) particularly in an off state is significantly decreased. Incontrast, there is no noticeable change in the peak value of themobility μ and the drain current I_(d) in an on state (on-statecurrent).

FIGS. 18A to 18C show the gate voltage V_(g) dependence of the draincurrent I_(d) (a solid line) and the mobility (a dotted line) of thetransistor where the offset length (the sidewall length) L_(off) is 5nm. The drain current I_(d) is obtained by calculation under theassumption that the drain voltage is +1 V and the mobility μ is obtainedby calculation under the assumption that the drain voltage is +0.1 V.FIG. 18A shows the gate voltage dependence of the transistor in the casewhere the thickness t of the gate insulating film is 15 nm, FIG. 18Bshows that of the transistor in the case where the thickness t of thegate insulating film is 10 nm, and FIG. 18C shows that of the transistorin the case where the thickness t of the gate insulating film is 5 nm.

Further, FIGS. 19A to 19C show the gate voltage dependence of the draincurrent I_(d) (a solid line) and the mobility μ (a dotted line) of thetransistor where the offset length (the sidewall length) L_(off) is 15nm. The drain current I_(d) is obtained by calculation under theassumption that the drain voltage V_(d) is +1 V and the mobility μ isobtained by calculation under the assumption that the drain voltage is+0.1 V. FIG. 19A shows the gate voltage dependence of the transistor inthe case where the thickness of the gate insulating film is 15 nm, FIG.19B shows that of the transistor in the case where the thickness of thegate insulating film is 10 nm, and FIG. 19C shows that of the transistorin the case where the thickness of the gate insulating film is 5 nm. Ineither of the structures, as the gate insulating film is thinner, theoff-state current is significantly decreased, whereas no noticeablechange arises in the peak value of the mobility μ and the on-statecurrent.

Note that the peak of the mobility μ is approximately 80 cm²/Vs in FIGS.17A to 17C, approximately 60 cm²/Vs in FIGS. 18A to 18C, andapproximately 40 cm²/Vs in FIGS. 19A to 19C; thus, the peak of themobility μ is decreased as the offset length L_(off) is increased.Further, the same applies to the off-state current. The on-state currentis also decreased as the offset length L_(off) is increased; however,the reduction in the on-state current is much more gradual than thereduction in off-state current. Further, any of the graphs shows thatthe drain current I_(d) exceeds 10 mA, which is needed for a memoryelement or the like, at a gate voltage V_(g) of around 1 V.

This embodiment can be implemented by being combined as appropriate withany of the above embodiments.

EXAMPLE 1

The memory device according to an embodiment of the present inventioncan operate at high speed, and has low power consumption, high storagecapacitance per unit area, and high reliability. Accordingly, by usingthe memory device according to an embodiment of the present invention,an electronic device with low power consumption, an electronic devicewhich can operate at high speed, a small electronic device, and a highlyreliable electronic device can be provided.

The memory device according to an embodiment of the present inventioncan be used for display devices, laptop personal computers, or imagereproducing devices provided with recording media (typically, deviceswhich reproduce the content of recording media such as digital versatilediscs (DVDs) and have displays for displaying the reproduced images).Other than the above, as an electronic device which can be provided withthe memory device according to an embodiment of the present invention,mobile phones, portable game machines, portable information terminals,e-book readers, video cameras, digital still cameras, goggle-typedisplays (head mounted displays), navigation systems, audio reproducingdevices (e.g., car audio systems and digital audio players), copiers,facsimiles, printers, multifunction printers, automated teller machines(ATM), vending machines, and the like can be given. Specific examples ofsuch electronic appliances are illustrated in FIGS. 11A to 11C.

FIG. 11A illustrates a portable game machine including a housing 7031, ahousing 7032, a display portion 7033, a display portion 7034, amicrophone 7035, speakers 7036, an operation key 7037, a stylus 7038,and the like. The memory device according to an embodiment of thepresent invention can be used for an integrated circuit for controllingdriving of the portable game machine. In that case, a portable gamemachine with low power consumption, a portable game machine which canoperate at high speed, a small portable game machine, or a highlyreliable portable game machine can be provided. Although the portablegame machine illustrated in FIG. 11A includes two display portions, thedisplay portion 7033 and the display portion 7034, the number of displayportions included in the portable game machine is not limited to two.

FIG. 11B illustrates a mobile phone including a housing 7041, a displayportion 7042, an audio input portion 7043, an audio output portion 7044,operation keys 7045, a light-receiving portion 7046, and the like. Lightreceived in the light-receiving portion 7046 is converted intoelectrical signals, whereby external images can be loaded. The memorydevice according to an embodiment of the present invention can be usedfor an integrated circuit for controlling driving of the mobile phone.In that case, a mobile phone with low power consumption, a mobile phonewhich can operate at high speed, a small mobile phone, or a highlyreliable mobile phone can be provided.

FIG. 11C illustrates a portable information terminal including a housing7051, a display portion 7052, operation keys 7053, and the like. A modemmay be incorporated in the housing 7051 of the portable informationterminal illustrated in FIG. 11C. The memory device according to anembodiment of the present invention can be used for an integratedcircuit for controlling driving of the portable information terminal. Inthat case, a portable information terminal with low power consumption, aportable information terminal which can operate at high speed, a smallportable information terminal, or a highly reliable portable informationterminal can be provided.

Example 1 can be implemented by being combined as appropriate with anyof the above embodiments.

EXAMPLE 2

A transistor including an oxide semiconductor containing In, Sn, and Zncan have favorable characteristics by deposition of the oxidesemiconductor while heating a substrate or by heat treatment afterdeposition of an oxide semiconductor film. Each of In, Sn, and Zn ispreferably contained in a composition ratio at greater than or equal to5 atomic %.

By heating the substrate after the deposition of the oxide semiconductorfilm containing In, Sn, and Zn, the mobility of the transistor can beimproved. The threshold voltage of an n-channel transistor can also beshifted in the positive direction. The positive shift of the thresholdvoltage of the n-channel transistor makes the absolute value of avoltage used for keeping the re-channel transistor off to decrease, sothat power consumption can be reduced. Further, the re-channeltransistor can become a normally-off transistor by a positive shift ofthe threshold voltage of the n-channel transistor such that thethreshold voltage is 0V or more.

Characteristics of transistors using the oxide semiconductor containingIn, Sn, and Zn are described below.

(Common Conditions of Samples A to C)

An oxide semiconductor film was formed over a substrate to have athickness of 15 nm under the following conditions: a target having acomposition ratio of In:Sn:Zn=1:1:1 is used; the gas flow rate isAr/O₂=6/9 sccm; the deposition pressure is 0.4 Pa; and the depositionpower is 100 W. Next, the oxide semiconductor film was etched in anisland shape. Then, a tungsten layer was deposited over the oxidesemiconductor layer to have a thickness of 50 nm, and was etched, sothat a source electrode and a drain electrode were formed.

Next, a silicon oxynitride film (SiON) was formed to have a thickness of100 nm, using silane gas (SiH₄) and dinitrogen monoxide (N₂O) by aplasma-enhanced CVD method, to form a gate insulating layer. Next, agate electrode was formed in the following manner a tantalum nitridelayer was formed to have a thickness of 15 nm; a tungsten layer wasformed to have a thickness of 135 nm; and the layers were etched.Further, a silicon oxynitride (SiON) film was formed so as to have athickness of 300 nm by a plasma-enhanced CVD method, and then, apolyimide film was formed so as to have a thickness of 1.5 μm, therebyforming an interlayer insulating film.

Next, a pad for measurement was formed in the following manner: acontact hole was formed in the interlayer insulating film; a firsttitanium film was formed to have a thickness of 50 nm; an aluminum filmwas formed to have a thickness of 100 nm; a second titanium film wasformed to have a thickness of 50 nm; and the films were etched.

In this manner, a semiconductor device having a transistor was formed.

(Sample A)

In Sample A, heating was not performed to the substrate during thedeposition of the oxide semiconductor film Further in Sample A, heattreatment was not performed after the deposition of the oxidesemiconductor film before the etching of the oxide semiconductor film.

(Sample B)

In Sample B, the oxide semiconductor film was deposited with thesubstrate heated at 200° C. Further in Sample B, heat treatment was notperformed after the deposition of the oxide semiconductor film beforethe etching of the oxide semiconductor film. The substrate was heatedwhile the oxide semiconductor film was deposited in order to removehydrogen serving as a donor in the oxide semiconductor film.

(Sample C)

In Sample C, the oxide semiconductor film was deposited with thesubstrate heated at 200° C. Further in Sample C, heat treatment in anitrogen atmosphere was performed at 650° C. for 1 hour and then heattreatment in an oxygen atmosphere was performed at 650° C. for 1 hourafter the oxide semiconductor film was deposited before the oxidesemiconductor film was etched. The heat treatment in a nitrogenatmosphere at 650° C. for 1 hour was performed in order to removehydrogen serving as a donor in the oxide semiconductor film.

Note that oxygen is also removed by the heat treatment used for removinghydrogen that serves as a donor in the oxide semiconductor film, causingoxygen deficiency which serves as a carrier in the oxide semiconductorfilm. Hence, an effect of reducing oxygen deficiencies was tried to beobtained by performing the heat treatment in an oxygen atmosphere at650° C. for 1 hour.

(Characteristics of Transistors of Sample A to Sample C)

FIG. 20A shows initial characteristics of a transistor of Sample A. FIG.20B shows initial characteristics of a transistor of Sample B. FIG. 20Cshows initial characteristics of a transistor of Sample C.

The mobility of the transistor of Sample A was 18.8 cm2/Vs. The mobilityof the transistor of Sample B was 32.2 cm²/Vs. The mobility of thetransistor of Sample C was 34.5 cm²/Vs.

According to observation of cross sections of oxide semiconductor filmswhich were formed by deposition methods similar to respective those ofSamples A to C, with a transmission electron microscope (TEM),crystallinity was observed in samples formed by the deposition methodssimilar to respective those of Sample B and Sample C, substrates ofwhich were heated during deposition.

Further, surprisingly, the samples, the substrates of which were heatedduring deposition, had a non-crystalline portion and a crystallineportion having a c-axis crystalline orientation. In a conventionalpolycrystal, the crystalline orientation in the crystalline portion isnot aligned. Therefore, it can be said that the sample, the substrate ofwhich was heated during deposition, has a novel crystal structure.

Comparison of FIGS. 20A to 20C brings understanding that heat treatmentperformed to the substrate during or after deposition can remove anhydrogen element serving as a donor, thereby shifting the thresholdvoltage of the n-channel transistor in the positive direction. That is,the threshold voltage of Sample B with heating of the substrate duringdeposition is shifted in the positive direction as compared to thethreshold voltage of Sample A without heating of the substrate duringdeposition.

In addition, it is found from comparison of Sample B and Sample C bothwith heating of the substrate during deposition that the thresholdvoltage of Sample C with the heat treatment after deposition is shiftedin the positive direction as compared to the threshold voltage of SampleB without the heat treatment after deposition. As the temperature ofheat treatment is higher, a light element such as hydrogen is removedmore easily; therefore, as the temperature of heat treatment is higher,hydrogen is removed more easily. Accordingly, it can be considered thatthe threshold voltage can be more shifted in the positive direction byfurther increasing the temperature of the heat treatment during or afterdeposition.

(Results of the Gate BT Stress Test of Sample B and Sample C)

A gate BT stress test was performed on Sample B (without heat treatmentafter deposition) and Sample C (with heat treatment after deposition).

First, V_(g)−I_(d) characteristics of each transistor were measured at asubstrate temperature of 25° C. and V_(d) of 10 V, whereby thecharacteristics of the transistor before heating and application of ahigh positive voltage were measured. Next, the substrate temperature wasset to 150° C. and V_(d) was set to 0.1 V. After that, 20 V was appliedas V_(g) to the gate insulating film, and was kept for 1 hour. Then,V_(g) was set to 0 V. Next, V_(g)−I_(d) characteristics of thetransistor were measured at a substrate temperature of 25° C. and V_(d)of 10 V, whereby the characteristics of the transistor after heating andapplication of a high positive voltage were measured.

Comparison of the characteristics of a transistor before and afterheating and application of a high positive voltage as described above isreferred to as a positive BT test.

On the other hand, first, V_(g)−I_(d) characteristics of each transistorwere measured at a substrate temperature of 25° C. and V_(d) of 10 V,whereby the characteristics of the transistor before heating andapplication of a high negative voltage were measured. Then, thesubstrate temperature was set to 150° C. and V_(d) was set to 0.1 V.Next, −20 V was applied as V_(g) to the gate insulating film, and waskept for 1 hour. Next, V_(g) was set to 0 V. Then, V_(g)−I_(d)characteristics of the transistor were measured at a substratetemperature of 25° C. and V_(d) of 10 V, whereby the characteristics ofthe transistor after heating and application of a high negative voltagewere measured.

Comparison of the characteristics of the transistor before and afterheating and application of a high negative voltage as described above isreferred to as a negative BT test.

FIG. 21A shows results of the positive BT test of Sample B, and FIG. 21Bshows results of the negative BT test of Sample B. FIG. 22A showsresults of the positive BT test of Sample C, and FIG. 22B shows resultsof the negative BT test of Sample C. Although the positive BT test andthe negative BT test are tests for determining the deterioration levelof a transistor, it is found from FIGS. 21A and 22A that the thresholdvoltage can be shifted in the positive direction by performing at leastthe positive BT test.

In particular, it is found that the positive BT test made the transistora normally-off transistor in FIG. 21A. Accordingly, it is found that,with the positive BT test as well as the heat treatment in manufacturingthe transistors, a shift of the threshold voltage in the positivedirection can be promoted and the transistor can be made to anormally-off transistor.

FIG. 23 shows a relation between the off-state current of the transistorof Sample A and the inverse of the substrate temperature (absolutetemperature) at measurement. In FIG. 23, the horizontal axis representsa value (1000/T) obtained by multiplying the inverse of the substratetemperature at measurement by 1000. The amount of current in FIG. 23 isthe amount of current per micrometer in the channel width.

The off-state current was lower than or equal to 1×10⁻¹⁹ A at asubstrate temperature of 125° C. (1000/T is about 2.51). The off-statecurrent was lower than or equal to 1×10⁻²⁰ A at a substrate temperatureof 85° C. (1000/T is about 3.66). In other words, it was found that theoff-state current is extremely low as compared to a transistor includinga silicon semiconductor. The off-state current is decreased as thetemperature decreases; therefore, it is clear that the off-state currentis lower at room temperature.

This application is based on Japanese Patent Application serial no.2011-013908 filed with Japan Patent Office on Jan. 26, 2011, andJapanese Patent Application serial no. 2011-108895 filed with JapanPatent Office on May 14, 2011, the entire contents of which are herebyincorporated by reference.

1. (canceled)
 2. A semiconductor device comprising: a circuit portion;an insulating film over the circuit portion; and a memory cell arrayover the insulating film, the memory cell array comprising: a pluralityof first memory cells positioned in a first region; a plurality ofsecond memory cells positioned in a second region; a plurality of thirdmemory cells positioned in a third region; a plurality of fourth memorycells positioned in a fourth region; a plurality of word lines; and aplurality of data lines, wherein the plurality of word lines iselectrically connected to the circuit portion through a plurality offirst contact holes, wherein the plurality of data lines is electricallyconnected to the circuit portion through a plurality of second contactholes, wherein the plurality of first contact holes are between thefirst region and the second region, and between the third region and thefourth region, wherein the plurality of second contact holes are betweenthe first region and the third region, and between the second region andthe fourth region, wherein the plurality of first contact holes arearranged along the plurality of data lines, and wherein the plurality ofsecond contact holes are arranged along the plurality of word lines. 3.The semiconductor device according to claim 2, wherein one of theplurality of first memory cells comprises a transistor, and wherein thetransistor comprises an oxide semiconductor film comprising a channelformation region.
 4. The semiconductor device according to claim 3,wherein the oxide semiconductor film comprises indium and zinc.
 5. Thesemiconductor device according to claim 3, wherein a hydrogenconcentration in the oxide semiconductor film is 1×10¹⁹/cm³ or less. 6.A semiconductor device comprising: a circuit portion; an insulating filmover the circuit portion; and a memory cell array over the insulatingfilm, the memory cell array comprising: a plurality of first memorycells positioned in a first region; a plurality of second memory cellspositioned in a second region; a plurality of word lines; and aplurality of data lines, wherein the plurality of word lines iselectrically connected to the circuit portion through a plurality ofcontact holes, wherein the plurality of data lines is electricallyconnected to the circuit portion, wherein the plurality of contact holesare between the first region and the second region, and wherein theplurality of contact holes are arranged along the plurality of datalines.
 7. The semiconductor device according to claim 6, wherein one ofthe plurality of first memory cells comprises a transistor, and whereinthe transistor comprises an oxide semiconductor film comprising achannel formation region.
 8. The semiconductor device according to claim7, wherein the oxide semiconductor film comprises indium and zinc. 9.The semiconductor device according to claim 7, wherein a hydrogenconcentration in the oxide semiconductor film is 1×10¹⁹/cm³ or less. 10.A semiconductor device comprising: a circuit portion; an insulating filmover the circuit portion; and a memory cell array over the insulatingfilm, the memory cell array comprising: a plurality of first memorycells positioned in a first region; a plurality of second memory cellspositioned in a second region; a plurality of word lines; and aplurality of data lines, wherein the plurality of word lines iselectrically connected to the circuit portion, wherein the plurality ofdata lines is electrically connected to the circuit portion through aplurality of contact holes, wherein the plurality of contact holes arebetween the first region and the second region, and wherein theplurality of contact holes are arranged along the plurality of wordlines.
 11. The semiconductor device according to claim 10, wherein oneof the plurality of first memory cells comprises a transistor, andwherein the transistor comprises an oxide semiconductor film comprisinga channel formation region.
 12. The semiconductor device according toclaim 11, wherein the oxide semiconductor film comprises indium andzinc.
 13. The semiconductor device according to claim 11, wherein ahydrogen concentration in the oxide semiconductor film is 1×10¹⁹/cm³ orless.